uart.h 4.6 KB

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  1. #ifndef UART_PRINT_H__
  2. #define UART_PRINT_H__
  3. /* UART Register Offsets. */
  4. #define UART_DR 0x00 /* Data read or written from the interface. */
  5. #define UART_RSR 0x04 /* Receive status register (Read). */
  6. #define UART_FR 0x18 /* Flag register (Read only). */
  7. #define UART_ILPR 0x20 /* IrDA low power counter register. */
  8. #define UART_IBRD 0x24 /* Integer baud rate divisor register. */
  9. #define UART_FBRD 0x28 /* Fractional baud rate divisor register. */
  10. #define UART_LCRH 0x2c /* Line control register. */
  11. #define UART_CR 0x30 /* Control register. */
  12. #define UART_IFLS 0x34 /* Interrupt fifo level select. */
  13. #define UART_IMSC 0x38 /* Interrupt mask. */
  14. #define UART_RIS 0x3c /* Raw interrupt status. */
  15. #define UART_MIS 0x40 /* Masked interrupt status. */
  16. #define UART_ICR 0x44 /* Interrupt clear register. */
  17. #define UART_DMACR 0x48 /* DMA control register. */
  18. #define UART_DR_OE (1 << 11)
  19. #define UART_DR_BE (1 << 10)
  20. #define UART_DR_PE (1 << 9)
  21. #define UART_DR_FE (1 << 8)
  22. #define UART_RSR_OE 0x08
  23. #define UART_RSR_BE 0x04
  24. #define UART_RSR_PE 0x02
  25. #define UART_RSR_FE 0x01
  26. #define UART_FR_RI 0x100
  27. #define UART_FR_TXFE 0x080
  28. #define UART_FR_RXFF 0x040
  29. #define UART_FR_TXFF 0x020
  30. #define UART_FR_RXFE 0x010
  31. #define UART_FR_BUSY 0x008
  32. #define UART_FR_DCD 0x004
  33. #define UART_FR_DSR 0x002
  34. #define UART_FR_CTS 0x001
  35. #define UART_FR_TMSK (UART_FR_TXFF + UART_FR_BUSY)
  36. #define UART_CR_CTSEN 0x8000 /* CTS hardware flow control */
  37. #define UART_CR_RTSEN 0x4000 /* RTS hardware flow control */
  38. #define UART_CR_OUT2 0x2000 /* OUT2 */
  39. #define UART_CR_OUT1 0x1000 /* OUT1 */
  40. #define UART_CR_RTS 0x0800 /* RTS */
  41. #define UART_CR_DTR 0x0400 /* DTR */
  42. #define UART_CR_RXE 0x0200 /* receive enable */
  43. #define UART_CR_TXE 0x0100 /* transmit enable */
  44. #define UART_CR_LBE 0x0080 /* loopback enable */
  45. #define UART_CR_RTIE 0x0040
  46. #define UART_CR_TIE 0x0020
  47. #define UART_CR_RIE 0x0010
  48. #define UART_CR_MSIE 0x0008
  49. #define UART_CR_IIRLP 0x0004 /* SIR low power mode */
  50. #define UART_CR_SIREN 0x0002 /* SIR enable */
  51. #define UART_CR_UARTEN 0x0001 /* UART enable */
  52. #define UART_LCRH_SPS 0x80
  53. #define UART_LCRH_WLEN_8 0x60
  54. #define UART_LCRH_WLEN_7 0x40
  55. #define UART_LCRH_WLEN_6 0x20
  56. #define UART_LCRH_WLEN_5 0x00
  57. #define UART_LCRH_FEN 0x10
  58. #define UART_LCRH_STP2 0x08
  59. #define UART_LCRH_EPS 0x04
  60. #define UART_LCRH_PEN 0x02
  61. #define UART_LCRH_BRK 0x01
  62. #define UART_IFLS_RX1_8 (0 << 3)
  63. #define UART_IFLS_RX2_8 (1 << 3)
  64. #define UART_IFLS_RX4_8 (2 << 3)
  65. #define UART_IFLS_RX6_8 (3 << 3)
  66. #define UART_IFLS_RX7_8 (4 << 3)
  67. #define UART_IFLS_TX1_8 (0 << 0)
  68. #define UART_IFLS_TX2_8 (1 << 0)
  69. #define UART_IFLS_TX4_8 (2 << 0)
  70. #define UART_IFLS_TX6_8 (3 << 0)
  71. #define UART_IFLS_TX7_8 (4 << 0)
  72. #define UART_OEIM (1 << 10) /* overrun error interrupt mask */
  73. #define UART_BEIM (1 << 9) /* break error interrupt mask */
  74. #define UART_PEIM (1 << 8) /* parity error interrupt mask */
  75. #define UART_FEIM (1 << 7) /* framing error interrupt mask */
  76. #define UART_RTIM (1 << 6) /* receive timeout interrupt mask */
  77. #define UART_TXIM (1 << 5) /* transmit interrupt mask */
  78. #define UART_RXIM (1 << 4) /* receive interrupt mask */
  79. #define UART_DSRMIM (1 << 3) /* DSR interrupt mask */
  80. #define UART_DCDMIM (1 << 2) /* DCD interrupt mask */
  81. #define UART_CTSMIM (1 << 1) /* CTS interrupt mask */
  82. #define UART_RIMIM (1 << 0) /* RI interrupt mask */
  83. #define UART_OEIS (1 << 10) /* overrun error interrupt status */
  84. #define UART_BEIS (1 << 9) /* break error interrupt status */
  85. #define UART_PEIS (1 << 8) /* parity error interrupt status */
  86. #define UART_FEIS (1 << 7) /* framing error interrupt status */
  87. #define UART_RTIS (1 << 6) /* receive timeout interrupt status */
  88. #define UART_TXIS (1 << 5) /* transmit interrupt status */
  89. #define UART_RXIS (1 << 4) /* receive interrupt status */
  90. #define UART_DSRMIS (1 << 3) /* DSR interrupt status */
  91. #define UART_DCDMIS (1 << 2) /* DCD interrupt status */
  92. #define UART_CTSMIS (1 << 1) /* CTS interrupt status */
  93. #define UART_RIMIS (1 << 0) /* RI interrupt status */
  94. #define CSIZE 0x0003
  95. #define CS8 0x0000
  96. #define CS6 0x0001
  97. #define CS7 0x0002
  98. #define CS5 0x0003
  99. #define CSTOPB 0x0004
  100. #define PARENB 0x0010
  101. #define PARODD 0x0020
  102. #define CMSPAR 0x0100 /* mark or space (stick) parity */
  103. #define CRTSCTS 0x0200 /* flow control */
  104. typedef enum {
  105. UART_ID0 = 0,
  106. UART_ID1,
  107. UART_ID2,
  108. UART_ID3,
  109. UART_NUM,
  110. } eUartID;
  111. void InitUart(unsigned int baud);
  112. void SendUartString(char * buf);
  113. void SendUartChar(char ch);
  114. void PrintVariableValueHex(char * variable, unsigned int value);
  115. void SendUartWord(unsigned int data);
  116. void IntToStr(unsigned int value, char *str);
  117. void uart_init(int id, unsigned int baud, unsigned int flags);
  118. void updateFromUart(int id);
  119. #endif