amt630h-sdk-beta/AMTLDR/Src/Entry.c

/*
**********************************************************************
Copyright (c)2009 Arkmicro Technologies Inc.  All Rights Reserved 
Filename: boot.c
Version : 1.00
Date    : 2010.06.29
Author  : Donier
Abstract: Ark2116 SoC boot rom code file.
Note    : The size the code(*.bin) loaded should never exceed 10K Bytes.
History : From the ark2116 SoC boot rom code file.
***********************************************************************
*/
#include "typedef.h"
#include "amt630h.h"
#include "BootModeSel.h"
#include "UartPrint.h"
#include "timer.h"
#include "mmu.h"
#include "sysinfo.h"
#include "spi.h"

#define PROJECT_FOR_DDR_INIT		0
#define PROJECT_FOR_SPINOR_LOADER	1
#define PROJECT_FOR_SD_UPDATE		2
#define PROJECT_FOR_JTAG_UPDATE		3

#define PROJECT_PURPOSE		PROJECT_FOR_DDR_INIT

#define SYSPLL_CLK  480//400//400//400//200 //336
#define CPUPLL_CLK  500//250//500//500//250 //500

// don't change is macro
#define DDR2_SRC_CLK_CPUPLL   	0
#define DDR2_SRC_CLK_SYSPLL   	1
#define DDR2_SRC_CLK_AUDPLL     2
#define DDR2_SRC_CLK_24M        4
#define DDR_TOTAL 0x400000   //8m x16

extern void SetSysPLL(unsigned int freq);
extern void SetCpuPLL(unsigned int freq);
extern void  SetXclkAHBclkAPBclk(void);
extern void SwitchTo24MHz(void);
extern void updateFromSD(int chipid);
extern void SpiNorBurn(void *buf, unsigned int offset, unsigned int size);
extern int wdt_init(void);

static void delay(volatile UINT32  count )
{
	while(count--);
}

void ddr_rd_clk_config()
{
  unsigned int  i;
  rSYS_DDRCTL1_CFG = 0x01;  //reset pll
  delay(1000);
  rSYS_DDRCTL1_CFG = 0x00;  //enable pll
  delay(100000);
  i = 0x01 << 1 | 200 << 8;
  rSYS_DDRCTL1_CFG = i;
  delay(100000);
}	

void ddr3_sdramc_init(void)
{
		
     unsigned long i;

	i = rSYS_DDRCTL1_CFG;
	i &= ~((0xFF << 24) |(0xFF << 16) | (0x7F << 8) | 0x7F);
	//i |= (0x40 << 24) |(0x40 << 8) | 0x40;
	rSYS_DDRCTL1_CFG = i;


    //ddr initialization
    //active_chip       qos      burst       stop     auto_power_down  power_down_cycle   ap_bit        row        col
#ifdef DDR16X16
	i = 0x0 << 21  | 0x0 <<18 | 0x2 << 15 | 0x0 <<14 |  0x0 <<13     |   0x0 << 7       |  0x0  <<6 |  0x2 <<3 |  0x1<< 0 ;  //16M*16
#else
     i = 0x0 << 21  | 0x0 <<18 | 0x2 << 15 | 0x0 <<14 |  0x0 <<13     |   0x0 << 7       |  0x0  <<0  |  0x1 <<3 |  0x1<< 0 ;  //8M*16
#endif
     MEM_CFG_REG = i ;
     //read_delay     mem_pro   mem_width  cke_init   dqm_init   clk_cfg  
     i = 0x6 << 9  | 0x1 <<6 | 0x0 << 4 | 0x1 <<3 |  0x0 <<2  |  0x00 << 0  ;  
     MEM_CFG2_REG = i ;
     //addr_fmt     addr_match   addr_mask

     //i = 0x1 << 16  | 0x80 <<8 | 0xff << 0 ;
     //CHIP_CFG_REG = i ;
    //early_resp
     i= 0x0 << 0;     
     FEA_CTL_REG = i ;
     //tref
#ifdef DDR16X16
     i= 380;
#else
     i= 1734;
#endif
     REF_PRD_REG = i ;
     //cas        //half cycle
     i= 0x3<<1 | 0x0<< 0;   //   
     TCAS_REG = i ;
     //tdqss
     i=  0x1<< 0;    
     TDQSS_REG = i ;
     //tmrd
     i=  0x2<< 0;    
     TMRD_REG = i ;
     //tras
     i=  0x8<< 0;
     TRAS_REG = i ;
     //trc
     i=  0xB << 0;
     TRC_REG = i ;
     //trcd        schelue rcd
     i=  0x3<< 0 | 0x3<<3;
     TRCD_REG = i ;
     //schelue trfc    trfc
     i=  15<<5|18<< 0;
     TRFC_REG = i ;
     //trp
     i=  0x3<< 0 | 0x3 << 3;
     TRP_REG = i ;
     //trrd
     i=  0x2<< 0;
     TRRD_REG = i ;
     //twr
     i=  0x3<< 0;
     TWR_REG = i ;
     //twtr
     i=  0x2<< 0;
     TWTR_REG = i ;
    //txp
     i=  0x1<< 0;
     TXP_REG = i ;
    //txsr
     i=  10<< 0;
     TXSR_REG = i ;
     //tesr
     i=  0x15<< 0;
     TESR_REG = i ;

    // 
    // //precharge
     DIR_CMD_REG = 0x000c0000 ;  //direct_cmd_reg nop
     DIR_CMD_REG = 0x00000000 ;  //direct_cmd_reg precharge
     DIR_CMD_REG = 0x00010000 ;  //direct_cmd_reg precharge
     DIR_CMD_REG = 0x00020000 ;  //direct_cmd_reg precharge
     DIR_CMD_REG = 0x00030000 ;  //direct_cmd_reg precharge
     DIR_CMD_REG = 0x00040000 ;  //direct_cmd_reg autorefresh
     DIR_CMD_REG = 0x00040000 ;  //direct_cmd_reg autorefresh
	 DIR_CMD_REG = 0x00090000 ;  //direct_cmd_reg exmodereg set
     DIR_CMD_REG = 0x00080032 ;  //direct_cmd_reg modereg set
     DIR_CMD_REG = 0x00030000 ;  //direct_cmd_reg precharge
	 DIR_CMD_REG = 0x00040000 ;  //direct_cmd_reg autorefresh
     DIR_CMD_REG = 0x00040000 ;  //direct_cmd_reg autorefresh
     DIR_CMD_REG = 0x000c0000 ;  //direct_cmd_reg nop

     MEM_CMD_REG = 0x00000000 ;  //mem_cmd_reg go
     while ((MEM_STA_REG &0x01)!=0x01) ;
}

void updateFromJtag(void)
{
	unsigned int loader_addr = 0x20000000;
	unsigned int stepldr_addr = 0x20010000;
	unsigned int app_addr = 0x20100000;
	UpFileHeader *header = (UpFileHeader *)app_addr;
	
	SendUartString("burn loader start... \r\n");
	SpiNorBurn((void*)loader_addr, LOADER_OFFSET, LOADER_MAX_SIZE);
	SendUartString("burn loader end. \r\n");
	
	SendUartString("burn stepldr start... \r\n");
	SpiNorBurn((void*)stepldr_addr, STEPLDRA_OFFSET, STEPLDR_MAX_SIZE);
	SendUartString("burn stepldr end. \r\n");	
	
	SendUartString("burn app start... \r\n");
	SpiNorBurn((void*)app_addr, IMAGE_OFFSET, header->size);
	SendUartString("burn app end. \r\n");
	
	SysInfo *sysinfo = GetSysInfo();
	sysinfo->app_checksum = header->checksum;
	sysinfo->stepldr_offset = STEPLDRA_OFFSET;
	sysinfo->stepldr_size = STEPLDR_MAX_SIZE;
	sysinfo->update_status = UPDATE_STATUS_END;
	SaveSysInfo(sysinfo);

	SendUartString("Update is finished. Please reset. \r\n");
	while(1);
}

void main(void)
{
	unsigned int val;

 	SwitchTo24MHz();
	
	timer_init();		
	InitUart(115200);
	SendUartString("\nARK AMT 630 H FROM SD V 1.21\r\n");

	val = rSYS_ANA1_CFG;
	val |= (1 << 4)|(5 << 1);
	rSYS_ANA1_CFG = val;
	udelay(300);
	val = rSYS_ANA1_CFG;
	val |= (0x1 <<5);
	rSYS_ANA1_CFG = val;
	val = rSYS_ANA2_CFG;
	val = (0x3F <<6)|(0 << 2)|(1 << 0);
	rSYS_ANA2_CFG = val;

    SetSysPLL(SYSPLL_CLK);
	SetCpuPLL(CPUPLL_CLK);
	udelay(500);
//	delay(600000);
	SetXclkAHBclkAPBclk();
	udelay(10);

#if PROJECT_PURPOSE == PROJECT_FOR_SPINOR_LOADER
	wdt_init();
#endif
	ddr3_sdramc_init();
	udelay(10);
	SendUartString("\nDDR init over2!!\r\n");
	
	SpiSelectPad();	
	SpiInit();

#ifdef MMU_ENABLE
	MMU_Init();
#endif

#if PROJECT_PURPOSE == PROJECT_FOR_DDR_INIT
	while(1);
#elif PROJECT_PURPOSE == PROJECT_FOR_SPINOR_LOADER	
	bootFromSPI();
#elif PROJECT_PURPOSE == PROJECT_FOR_SD_UPDATE
	SetDefaultSysInfo();
	SaveSysInfo(0);
	updateFromSD(0);
	bootFromSPI();
#elif PROJECT_PURPOSE == PROJECT_FOR_JTAG_UPDATE
	updateFromJtag();
#endif
}