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CommonDef.inc

CommonDef.inc 2.0 KB
Cronologia Originale

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  1. ;Pre-defined run mode constants
    2. 

  2. USERMODE    		EQU 	0x10
    3. 

  3. FIQMODE     		EQU 	0x11
    4. 

  4. IRQMODE     		EQU 	0x12
    5. 

  5. SVCMODE     		EQU 	0x13
    6. 

  6. ABORTMODE   		EQU 	0x17
    7. 

  7. UNDEFMODE   		EQU 	0x1b
    8. 

  8. MODEMASK    		EQU 	0x1f
    9. 

  9. NOINT       		EQU 	0xc0
    10. 

  10. 

  11. 

  12. ;Stacks defination for each run mode
    13. 

  13. _STACK_BASEADDRESS	EQU		0xC0008000
    14. 

  14. 

  15. UserStackLen		EQU		0x10
    16. 

  16. SVCStackLen			EQU		0x2000
    17. 

  17. UndefStackLen		EQU		0x10
    18. 

  18. AbortStackLen		EQU		0x10
    19. 

  19. IRQStackLen			EQU		0x400
    20. 

  20. FIQStackLen			EQU		0x10
    21. 

  21. 

  22. UserStackStart		EQU		(_STACK_BASEADDRESS)      
    23. 

  23. UndefStackStart		EQU		(UserStackStart - UserStackLen) 
    24. 

  24. AbortStackStart		EQU		(UndefStackStart - UndefStackLen) 
    25. 

  25. IRQStackStart		EQU		(AbortStackStart - AbortStackLen) 
    26. 

  26. FIQStackStart		EQU		(IRQStackStart - IRQStackLen) 
    27. 

  27. SVCStackStart		EQU		(FIQStackStart - FIQStackLen) 
    28. 

  28. 

  29. 

  30. VICL_BASE			EQU		0xE0C00000
    31. 

  31. VICH_BASE			EQU		0xE0B00000
    32. 

  32. ENABLE_REG_OFFSET	EQU		0x10
    33. 

  33. CLR_REG_OFFSET		EQU		0x14
    34. 

  34. ADDRESS_REG_OFFSET	EQU		0xF00
    35. 

  35. VICL_RAW_STATUS   	EQU		0xE0C00008    ;Interrupt raw status low 32 vector
    36. 

  36. VICH_RAW_STATUS   	EQU		0xE0B00008    ;Interrupt raw status high 32 vector
    37. 

  37. VICL_SEL_REG   		EQU		0xE0C0000C    ;Interrupt select reg for low 32 vector
    38. 

  38. VICH_SEL_REG   		EQU		0xE0B0000C    ;Interrupt select reg for high 32 vector
    39. 

  39. VICL_ENABLE			EQU		0xE0C00010    ;Interrupt Enable control low 32 vector
    40. 

  40. VICH_ENABLE			EQU		0xE0B00010    ;Interrupt Enable control high 32 vector
    41. 

  41. VICL_CLR			EQU		0xE0C00014    ;Interrupt clear control low 32 vector
    42. 

  42. VICH_CLR			EQU		0xE0B00014    ;Interrupt clear control high 32 vector
    43. 

  43. VICL_ADDR_BASE		EQU		0xE0C00100    
    44. 

  44. VICH_ADDR_BASE		EQU		0xE0B00100    
    45. 

  45. VICL_PROORITY_BASE	EQU		0xE0C00200
    46. 

  46. VICH_PROORITY_BASE	EQU		0xE0B00200
    47. 

  47. 

  48. ;ENABLE_VE			EQU		0x01000000	
    49. 

  49. VICL_ADDRESS 		EQU 	0xE0C00F00
    50. 

  50. VICH_ADDRESS 		EQU 	0xE0B00F00
    51. 

  51. 

  52. 

  53. WDT_CTL			EQU		0xE4B00000
    54. 

  54. 

  55. ITCM0_BaseAddress		EQU		0xA0000000	;ITCM0 base : 0xA0000000, Size : 8KB,
    56. 

  56. ITCM1_BaseAddress		EQU		0xA0002000	;ITCM1 base : 0xA0002000, Size : 8KB,
    57. 

  57. DTCM0_BaseAddress		EQU		0xA0004000	;DTCM0 base : 0xA0004000, Size : 8KB,
    58. 

  58. DTCM1_BaseAddress		EQU		0xA0006000	;DTCM1 base : 0xA0006000, Size : 8KB,
    59.