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CommonDef.inc

CommonDef.inc 2.1 KB
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  1.  //#define VECTOR_ENABLE	TRUE
    2. 

  2.  #define	VECTOR_ENABLE	FALSE
    3. 

  3. 

  4. ;Pre-defined run mode constants
    5. 

  5. USERMODE    		EQU 	0x10
    6. 

  6. FIQMODE     		EQU 	0x11
    7. 

  7. IRQMODE     		EQU 	0x12
    8. 

  8. SVCMODE     		EQU 	0x13
    9. 

  9. ABORTMODE   		EQU 	0x17
    10. 

  10. UNDEFMODE   		EQU 	0x1b
    11. 

  11. MODEMASK    		EQU 	0x1f
    12. 

  12. NOINT       		EQU 	0xc0
    13. 

  13. 

  14. 

  15. ;Stacks defination for each run mode
    16. 

  16. _STACK_BASEADDRESS	EQU		0xC0008000
    17. 

  17. 

  18. UserStackLen		EQU		0x10
    19. 

  19. SVCStackLen			EQU		0x2000
    20. 

  20. UndefStackLen		EQU		0x10
    21. 

  21. AbortStackLen		EQU		0x10
    22. 

  22. IRQStackLen			EQU		0x400
    23. 

  23. FIQStackLen			EQU		0x10
    24. 

  24. 

  25. UserStackStart		EQU		(_STACK_BASEADDRESS)      
    26. 

  26. UndefStackStart		EQU		(UserStackStart - UserStackLen) 
    27. 

  27. AbortStackStart		EQU		(UndefStackStart - UndefStackLen) 
    28. 

  28. IRQStackStart		EQU		(AbortStackStart - AbortStackLen) 
    29. 

  29. FIQStackStart		EQU		(IRQStackStart - IRQStackLen) 
    30. 

  30. SVCStackStart		EQU		(FIQStackStart - FIQStackLen) 
    31. 

  31. 

  32. 

  33. VICL_BASE			EQU		0xE0C00000
    34. 

  34. VICH_BASE			EQU		0xE0B00000
    35. 

  35. ENABLE_REG_OFFSET	EQU		0x10
    36. 

  36. CLR_REG_OFFSET		EQU		0x14
    37. 

  37. ADDRESS_REG_OFFSET	EQU		0xF00
    38. 

  38. VICL_RAW_STATUS   	EQU		0xE0C00008    ;Interrupt raw status low 32 vector
    39. 

  39. VICH_RAW_STATUS   	EQU		0xE0B00008    ;Interrupt raw status high 32 vector
    40. 

  40. VICL_SEL_REG   		EQU		0xE0C0000C    ;Interrupt select reg for low 32 vector
    41. 

  41. VICH_SEL_REG   		EQU		0xE0B0000C    ;Interrupt select reg for high 32 vector
    42. 

  42. VICL_ENABLE			EQU		0xE0C00010    ;Interrupt Enable control low 32 vector
    43. 

  43. VICH_ENABLE			EQU		0xE0B00010    ;Interrupt Enable control high 32 vector
    44. 

  44. VICL_CLR			EQU		0xE0C00014    ;Interrupt clear control low 32 vector
    45. 

  45. VICH_CLR			EQU		0xE0B00014    ;Interrupt clear control high 32 vector
    46. 

  46. VICL_ADDR_BASE		EQU		0xE0C00100    
    47. 

  47. VICH_ADDR_BASE		EQU		0xE0B00100    
    48. 

  48. VICL_PROORITY_BASE	EQU		0xE0C00200
    49. 

  49. VICH_PROORITY_BASE	EQU		0xE0B00200
    50. 

  50. 

  51. ;ENABLE_VE			EQU		0x01000000	
    52. 

  52. VICL_ADDRESS 		EQU 	0xE0C00F00
    53. 

  53. VICH_ADDRESS 		EQU 	0xE0B00F00
    54. 

  54. 

  55. 

  56. WDT_CTL			EQU		0xE4B00000
    57. 

  57. 

  58. ITCM0_BaseAddress		EQU		0xA0000000	;ITCM0 base : 0xA0000000, Size : 8KB,
    59. 

  59. ITCM1_BaseAddress		EQU		0xA0002000	;ITCM1 base : 0xA0002000, Size : 8KB,
    60. 

  60. DTCM0_BaseAddress		EQU		0xA0004000	;DTCM0 base : 0xA0004000, Size : 8KB,
    61. 

  61. DTCM1_BaseAddress		EQU		0xA0006000	;DTCM1 base : 0xA0006000, Size : 8KB,
    62.