core_intr.c 8.0 KB

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  1. /*
  2. * core_intr.c - DesignWare HS OTG Controller common interrupt handling
  3. *
  4. * Copyright (C) 2004-2013 Synopsys, Inc.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions
  8. * are met:
  9. * 1. Redistributions of source code must retain the above copyright
  10. * notice, this list of conditions, and the following disclaimer,
  11. * without modification.
  12. * 2. Redistributions in binary form must reproduce the above copyright
  13. * notice, this list of conditions and the following disclaimer in the
  14. * documentation and/or other materials provided with the distribution.
  15. * 3. The names of the above-listed copyright holders may not be used
  16. * to endorse or promote products derived from this software without
  17. * specific prior written permission.
  18. *
  19. * ALTERNATIVELY, this software may be distributed under the terms of the
  20. * GNU General Public License ("GPL") as published by the Free Software
  21. * Foundation; either version 2 of the License, or (at your option) any
  22. * later version.
  23. *
  24. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  25. * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  26. * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  27. * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  28. * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  29. * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  30. * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  31. * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  32. * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  33. * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  34. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35. */
  36. /*
  37. * This file contains the common interrupt handlers
  38. */
  39. #include "usb_os_adapter.h"
  40. #include "trace.h"
  41. #include <asm/dma-mapping.h>
  42. #include <linux/usb/ch9.h>
  43. #include <linux/usb/gadget.h>
  44. #include "core.h"
  45. #include "hcd.h"
  46. const char *dwc2_op_state_str(struct dwc2_hsotg *hsotg)
  47. {
  48. switch (hsotg->op_state) {
  49. case OTG_STATE_A_HOST:
  50. return "a_host";
  51. case OTG_STATE_A_SUSPEND:
  52. return "a_suspend";
  53. case OTG_STATE_A_PERIPHERAL:
  54. return "a_peripheral";
  55. case OTG_STATE_B_PERIPHERAL:
  56. return "b_peripheral";
  57. case OTG_STATE_B_HOST:
  58. return "b_host";
  59. default:
  60. return "unknown";
  61. }
  62. }
  63. /**
  64. * dwc2_handle_mode_mismatch_intr() - Logs a mode mismatch warning message
  65. *
  66. * @hsotg: Programming view of DWC_otg controller
  67. */
  68. static void dwc2_handle_mode_mismatch_intr(struct dwc2_hsotg *hsotg)
  69. {
  70. /* Clear interrupt */
  71. dwc2_writel(GINTSTS_MODEMIS, hsotg->regs + GINTSTS);
  72. dev_warn(hsotg->dev, "Mode Mismatch Interrupt: currently in %s mode\n",
  73. dwc2_is_host_mode(hsotg) ? "Host" : "Device");
  74. }
  75. /**
  76. * dwc2_handle_otg_intr() - Handles the OTG Interrupts. It reads the OTG
  77. * Interrupt Register (GOTGINT) to determine what interrupt has occurred.
  78. *
  79. * @hsotg: Programming view of DWC_otg controller
  80. */
  81. static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg)
  82. {
  83. u32 gotgint;
  84. gotgint = dwc2_readl(hsotg->regs + GOTGINT);
  85. /* Clear GOTGINT */
  86. dwc2_writel(gotgint, hsotg->regs + GOTGINT);
  87. }
  88. /**
  89. * dwc2_handle_conn_id_status_change_intr() - Handles the Connector ID Status
  90. * Change Interrupt
  91. *
  92. * @hsotg: Programming view of DWC_otg controller
  93. *
  94. * Reads the OTG Interrupt Register (GOTCTL) to determine whether this is a
  95. * Device to Host Mode transition or a Host to Device Mode transition. This only
  96. * occurs when the cable is connected/removed from the PHY connector.
  97. */
  98. static void dwc2_handle_conn_id_status_change_intr(struct dwc2_hsotg *hsotg)
  99. {
  100. u32 gintmsk;
  101. /* Clear interrupt */
  102. dwc2_writel(GINTSTS_CONIDSTSCHNG, hsotg->regs + GINTSTS);
  103. /* Need to disable SOF interrupt immediately */
  104. gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
  105. gintmsk &= ~GINTSTS_SOF;
  106. dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
  107. dev_dbg(hsotg->dev, " ++Connector ID Status Change Interrupt++ (%s)\n",
  108. dwc2_is_host_mode(hsotg) ? "Host" : "Device");
  109. }
  110. /**
  111. * dwc2_handle_session_req_intr() - This interrupt indicates that a device is
  112. * initiating the Session Request Protocol to request the host to turn on bus
  113. * power so a new session can begin
  114. *
  115. * @hsotg: Programming view of DWC_otg controller
  116. *
  117. * This handler responds by turning on bus power. If the DWC_otg controller is
  118. * in low power mode, this handler brings the controller out of low power mode
  119. * before turning on bus power.
  120. */
  121. static void dwc2_handle_session_req_intr(struct dwc2_hsotg *hsotg)
  122. {
  123. /* Clear interrupt */
  124. dwc2_writel(GINTSTS_SESSREQINT, hsotg->regs + GINTSTS);
  125. dev_dbg(hsotg->dev, "Session request interrupt - lx_state=%d\n",
  126. hsotg->lx_state);
  127. }
  128. /*
  129. * This interrupt indicates that a device has been disconnected from the
  130. * root port
  131. */
  132. static void dwc2_handle_disconnect_intr(struct dwc2_hsotg *hsotg)
  133. {
  134. dwc2_writel(GINTSTS_DISCONNINT, hsotg->regs + GINTSTS);
  135. dev_dbg(hsotg->dev, "++Disconnect Detected Interrupt++ (%s) %s\n",
  136. dwc2_is_host_mode(hsotg) ? "Host" : "Device",
  137. dwc2_op_state_str(hsotg));
  138. if (hsotg->op_state == OTG_STATE_A_HOST)
  139. dwc2_hcd_disconnect(hsotg, false);
  140. }
  141. /*
  142. * This interrupt indicates that SUSPEND state has been detected on the USB.
  143. *
  144. * For HNP the USB Suspend interrupt signals the change from "a_peripheral"
  145. * to "a_host".
  146. *
  147. * When power management is enabled the core will be put in low power mode.
  148. */
  149. static void dwc2_handle_usb_suspend_intr(struct dwc2_hsotg *hsotg)
  150. {
  151. /* Clear interrupt */
  152. dwc2_writel(GINTSTS_USBSUSP, hsotg->regs + GINTSTS);
  153. dev_dbg(hsotg->dev, "USB SUSPEND\n");
  154. if (hsotg->op_state == OTG_STATE_A_PERIPHERAL) {
  155. dev_dbg(hsotg->dev, "a_peripheral->a_host\n");
  156. /* Change to L2 (suspend) state */
  157. hsotg->lx_state = DWC2_L2;
  158. /* Clear the a_peripheral flag, back to a_host */
  159. spin_unlock(&hsotg->lock);
  160. dwc2_hcd_start_isr(hsotg);
  161. spin_lock(&hsotg->lock);
  162. hsotg->op_state = OTG_STATE_A_HOST;
  163. }
  164. }
  165. #define GINTMSK_COMMON (GINTSTS_WKUPINT | GINTSTS_SESSREQINT | \
  166. GINTSTS_CONIDSTSCHNG | GINTSTS_OTGINT | \
  167. GINTSTS_MODEMIS | GINTSTS_DISCONNINT | \
  168. GINTSTS_USBSUSP | GINTSTS_PRTINT)
  169. /*
  170. * This function returns the Core Interrupt register
  171. */
  172. static u32 dwc2_read_common_intr(struct dwc2_hsotg *hsotg)
  173. {
  174. u32 gintsts;
  175. u32 gintmsk;
  176. u32 gahbcfg;
  177. u32 gintmsk_common = GINTMSK_COMMON;
  178. gintsts = dwc2_readl(hsotg->regs + GINTSTS);
  179. gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
  180. gahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
  181. /* If any common interrupts set */
  182. if (gintsts & gintmsk_common)
  183. dev_dbg(hsotg->dev, "gintsts=%08x gintmsk=%08x\n",
  184. gintsts, gintmsk);
  185. if (gahbcfg & GAHBCFG_GLBL_INTR_EN)
  186. return gintsts & gintmsk & gintmsk_common;
  187. else
  188. return 0;
  189. }
  190. /*
  191. * Common interrupt handler
  192. *
  193. * The common interrupts are those that occur in both Host and Device mode.
  194. * This handler handles the following interrupts:
  195. * - Mode Mismatch Interrupt
  196. * - OTG Interrupt
  197. * - Connector ID Status Change Interrupt
  198. * - Disconnect Interrupt
  199. * - Session Request Interrupt
  200. * - Resume / Remote Wakeup Detected Interrupt
  201. * - Suspend Interrupt
  202. */
  203. irqreturn_t dwc2_handle_common_intr(int irq, void *dev)
  204. {
  205. struct dwc2_hsotg *hsotg = dev;
  206. u32 gintsts;
  207. irqreturn_t retval = IRQ_NONE;
  208. if (!dwc2_is_controller_alive(hsotg)) {
  209. dev_warn(hsotg->dev, "Controller is dead\n");
  210. goto out;
  211. }
  212. gintsts = dwc2_read_common_intr(hsotg);
  213. if (gintsts & ~GINTSTS_PRTINT)
  214. retval = IRQ_HANDLED;
  215. if (gintsts & GINTSTS_MODEMIS)
  216. dwc2_handle_mode_mismatch_intr(hsotg);
  217. if (gintsts & GINTSTS_OTGINT)
  218. dwc2_handle_otg_intr(hsotg);
  219. if (gintsts & GINTSTS_CONIDSTSCHNG)
  220. dwc2_handle_conn_id_status_change_intr(hsotg);
  221. if (gintsts & GINTSTS_DISCONNINT)
  222. dwc2_handle_disconnect_intr(hsotg);
  223. if (gintsts & GINTSTS_SESSREQINT)
  224. dwc2_handle_session_req_intr(hsotg);
  225. if (gintsts & GINTSTS_USBSUSP)
  226. dwc2_handle_usb_suspend_intr(hsotg);
  227. if (gintsts & GINTSTS_PRTINT) {
  228. /*
  229. * The port interrupt occurs while in device mode with HPRT0
  230. * Port Enable/Disable
  231. */
  232. }
  233. out:
  234. return retval;
  235. }