SpinandBooter.c 31 KB

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  1. #include "typedef.h"
  2. #include "atm630h.h"
  3. #define MAX_WAIT_LOOP_COUNT 100000
  4. #define LITTLE_ENDIAN
  5. #define SPI_WRITE_ENABLE 0x06
  6. #define SPI_WRITE_DISABLE 0x04
  7. #define SPI_READ_STATUS 0x05
  8. #define SPI_READ_STATUS2 0x35
  9. #define SPI_READ_STATUS3 0x15
  10. #define SPI_WRITE_STATUS 0x01
  11. #define SPI_WRITE_STATUS2 0x31
  12. #define SPI_WRITE_STATUS3 0x11
  13. #define SPI_READ_DATA 0x03
  14. #define SPI_FAST_READ 0x0B
  15. #define SPI_PAGE_PROGRAM 0x02
  16. #define SPI_SECTOR_ERASE 0x20
  17. #define SPI_SECTOR_ERASE_1 0xD7
  18. #define SPI_BLOCK_ERASE 0xD8
  19. #define SPI_BLOCK_ERASE_1 0x52
  20. #define SPI_CHIP_ERASE 0xC7
  21. #define SPI_CHIP_ERASE_1 0x60
  22. #define SPI_POWER_DOWN 0xB9
  23. #define SPI_READ_JEDEC_ID 0x9F
  24. #define SPI_READ_ID_1 0xAB
  25. #define SPI_MF_DEVICE_ID 0x90
  26. #define SPI_MF_DEVICE_ID_1 0x15
  27. #define SPI_READ_ELECTRON_SIGN 0xAB
  28. #define SPI_4READ_MODE0 0xEB
  29. #define SPI_4WRITE_MODE 0x32
  30. #define SPI_4READ_MODE1 0x6B
  31. #define SPI_MF_WINBOND 0xEF
  32. #define SPI_MF_EON 0x1C
  33. #define SPI_MF_AMIC 0x37
  34. #define SPI_MF_ATMEL 0x1F
  35. #define SPI_MF_SST 0xBF
  36. #define SPI_MF_MXIC 0xC2
  37. #define SPI_RXFIFO_ENABLE (1<<8)
  38. #define SPI_TRANS_COMPLETE (1<<7)
  39. #define SPI_RXFIFO_OVER (1<<6)
  40. #define SPI_TXFIFO_FULL (1<<2)
  41. #define SPI_TXFIFO_REQ (1<<1)
  42. #define SPI_RXFIFO_FULL (1<<4)
  43. #define SPI_RXFIFO_NOTEMPTY (1<<3)
  44. #define SPI_TXFIFO_EMPTY (1<<2)
  45. #define SPI_TXFIFO_NOTFULL (1<<1)
  46. #define SPI_BUSY (1<<0)
  47. #define SPIFLASH_BUSY (1<<0)
  48. #define SPIFLASH_WRITEENABLE (1<<1)
  49. #define STANDARDFORMAT 0
  50. #define DUALFORMAT 1
  51. #define QUADFORMAT 2
  52. #define READ_WRITE 0
  53. #define READ_ONLY 2
  54. #define WRITE_ONLY 1
  55. #define STRANDARD_MODE 0
  56. #define ADDR_4BYTES 1
  57. #define BOTH_4BYTES 2
  58. #define WORDSPERPAGE 64
  59. #define BYTESPERPAGE 256
  60. #define PAGESPERSECTORS 16
  61. #define SECTORSPERBLOCK 16
  62. #define BLOCKSPERFLASH 16//64
  63. //#define WORDSPERPAGE 64
  64. //#define BYTESPERPAGE 256
  65. //#define PAGESPERSECTORS 16
  66. //#define SECTORSPERBLOCK 16
  67. //#define BLOCKSPERFLASH 256
  68. #define BYTESPERBLOCK (BYTESPERPAGE*PAGESPERSECTORS*SECTORSPERBLOCK)
  69. #define BYTESPERSECTOR (BYTESPERPAGE*PAGESPERSECTORS)
  70. #define SPI_DMA_ENABLE 1
  71. #define GPIO101 101
  72. static void delay(unsigned int time)
  73. {
  74. volatile unsigned int count = time;
  75. while(count--);
  76. }
  77. void SpiSetFrameFormatMode(unsigned char format,unsigned char tmod);
  78. void TestSpiInterrupt(void);
  79. static void SetCSGpioEnable(int enable)
  80. {
  81. // rSYS_PAD_CTRL0A &= ~((0x7<<3));
  82. // SetGPIODataDirection(GPIO101,euOutputPad);
  83. // SetGPIOPadData(GPIO101, !enable);
  84. rSYS_PAD_CTRL02 &= ~(0x3<<0);
  85. *((volatile unsigned int *)(0x60900000+0x84)) |= (0x1 << 0);
  86. if(!enable)
  87. *((volatile unsigned int *)(0x60900000+0x80)) |= (0x1 << 0);
  88. else
  89. *((volatile unsigned int *)(0x60900000+0x80)) &= ~(0x1 << 0);
  90. }
  91. static void SetSpiDataMode(unsigned int bitMode)
  92. {
  93. unsigned int val = 0;
  94. while((rSPI_SR & SPI_BUSY));
  95. rSPI_SSIENR = 0;
  96. val = rSPI_CTLR0;
  97. val &=~(0x1f<<16);
  98. val |=((bitMode-1)<<16);
  99. rSPI_CTLR0 = val;
  100. rSPI_SSIENR = 1;
  101. }
  102. static void SetSpiRevNDF(unsigned int ndf)
  103. {
  104. while((rSPI_SR & SPI_BUSY));
  105. rSPI_SSIENR = 0;
  106. rSPI_CTLR1 = ndf & 0xffff;
  107. rSPI_SSIENR = 1;
  108. }
  109. static void SpiEmptyRxFIFO(void)
  110. {
  111. INT32 data = 0;
  112. while(rSPI_SR & SPI_RXFIFO_NOTEMPTY)
  113. {
  114. data = rSPI_DR;
  115. }
  116. }
  117. static UINT8 SpiReadSta(void)
  118. {
  119. UINT8 status;
  120. SetSpiDataMode(8);
  121. rSPI_DR = SPI_READ_STATUS;
  122. rSPI_DR = 0;
  123. while(!(rSPI_SR & SPI_RXFIFO_NOTEMPTY));
  124. status = rSPI_DR;
  125. while(!(rSPI_SR & SPI_RXFIFO_NOTEMPTY));
  126. status = rSPI_DR;
  127. SetSpiDataMode(32);
  128. return status;
  129. }
  130. static UINT8 SpiReadSta2(void)
  131. {
  132. UINT8 status;
  133. SetSpiDataMode(8);
  134. rSPI_DR = SPI_READ_STATUS2;
  135. rSPI_DR = 0;
  136. while(!(rSPI_SR & SPI_RXFIFO_NOTEMPTY));
  137. status = rSPI_DR;
  138. while(!(rSPI_SR & SPI_RXFIFO_NOTEMPTY));
  139. status = rSPI_DR;
  140. SetSpiDataMode(32);
  141. return status;
  142. }
  143. static UINT8 SpiReadSta3(void)
  144. {
  145. UINT8 status;
  146. SetSpiDataMode(8);
  147. rSPI_DR = SPI_READ_STATUS3;
  148. rSPI_DR = 0;
  149. while(!(rSPI_SR & SPI_RXFIFO_NOTEMPTY));
  150. status = rSPI_DR;
  151. while(!(rSPI_SR & SPI_RXFIFO_NOTEMPTY));
  152. status = rSPI_DR;
  153. SetSpiDataMode(32);
  154. return status;
  155. }
  156. void SpiWriteEnable(void)
  157. {
  158. SetSpiDataMode(8);
  159. rSPI_DR = SPI_WRITE_ENABLE;
  160. while((SpiReadSta() & SPIFLASH_BUSY));
  161. while(!(SpiReadSta() & SPIFLASH_WRITEENABLE));
  162. SetSpiDataMode(32);
  163. }
  164. void SpiWriteDisable(void)
  165. {
  166. SetSpiDataMode(8);
  167. rSPI_DR = SPI_WRITE_DISABLE;
  168. while((SpiReadSta() & SPIFLASH_BUSY));
  169. while((SpiReadSta() & SPIFLASH_WRITEENABLE));
  170. SetSpiDataMode(32);
  171. }
  172. static UINT8 SpiWriteSta(unsigned char state)
  173. {
  174. SpiWriteEnable();
  175. SetSpiDataMode(8);
  176. rSPI_DR = SPI_WRITE_STATUS;
  177. rSPI_DR = state;
  178. while((SpiReadSta() & SPIFLASH_BUSY));
  179. SetSpiDataMode(32);
  180. }
  181. static UINT8 SpiWriteSta2(unsigned char state)
  182. {
  183. SpiWriteEnable();
  184. SetSpiDataMode(8);
  185. rSPI_DR = SPI_WRITE_STATUS2;
  186. rSPI_DR = state;
  187. while((SpiReadSta() & SPIFLASH_BUSY));
  188. SetSpiDataMode(32);
  189. }
  190. static UINT8 SpiWriteSta3(unsigned char state)
  191. {
  192. SpiWriteEnable();
  193. SetSpiDataMode(8);
  194. rSPI_DR = SPI_WRITE_STATUS3;
  195. rSPI_DR = state;
  196. while((SpiReadSta() & SPIFLASH_BUSY));
  197. SetSpiDataMode(32);
  198. }
  199. static void SpiSelectPad()
  200. {
  201. UINT32 val;
  202. val = rSYS_PAD_CTRL02;
  203. val &= ~(0xfff);
  204. // val |= (0x1<<10)|(0x1 << 8)|(0x1 << 6)|(0x1 << 4)| (0x1 << 2)| (0x1 << 0);
  205. val |= (0x1 << 6)|(0x1 << 4)| (0x1 << 2)| (0x1 << 0);
  206. rSYS_PAD_CTRL02 = val;
  207. val = rSYS_SSP_CLK_CFG;
  208. val &= ~((0x1<<31)|(0x1<<30));
  209. val |= (0x1<<31)|(0x1<<30);
  210. rSYS_SSP_CLK_CFG = val;
  211. *((volatile unsigned int *)(0x60900000+0x84)) |= (0x1 << 4);
  212. *((volatile unsigned int *)(0x60900000+0x84)) |= (0x1 << 5);
  213. *((volatile unsigned int *)(0x60900000+0x80)) |= (0x1 << 5);
  214. *((volatile unsigned int *)(0x60900000+0x80)) |= (0x1 << 4);
  215. // rSYS_SSP_CLK_CFG |= (0x1 << 4) ;
  216. rSYS_BUS_CLK_SEL |= (0x1 << 16);
  217. }
  218. static void SpiInit()
  219. {
  220. rSPI_SSIENR = 0;
  221. rSPI_CTLR0 = 0;
  222. rSPI_CTLR0 |=(0<<21)|(0x1f<<16)|(0x0<<12)|(0x0<<8)|(0x0<<4);
  223. // rSPI_CTLR1 = 63;
  224. rSPI_BAUDR = 2;//16;//2;
  225. rSPI_SER = 1;
  226. rSPI_SSIENR = 1;
  227. SetCSGpioEnable(0);
  228. }
  229. static void SpiReadDeviceId(UINT8 *mfid, UINT8 *devid)
  230. {
  231. UINT8 val[6];
  232. int i;
  233. SetSpiDataMode(8);
  234. rSPI_DR = SPI_MF_DEVICE_ID;
  235. rSPI_DR = 0;
  236. rSPI_DR = 0;
  237. rSPI_DR = 0;
  238. rSPI_DR = 0;
  239. rSPI_DR = 0;
  240. for (i = 0; i < 6; i++)
  241. {
  242. while(!(rSPI_SR & SPI_RXFIFO_NOTEMPTY));
  243. val[i] = rSPI_DR;
  244. }
  245. *mfid = val[4];
  246. *devid = val[5];
  247. SetSpiDataMode(32);
  248. }
  249. #if 1
  250. /*******************************************************************************
  251. *正常
  252. * SpiDmaRead 能正常读取
  253. *
  254. * 参数 *buf 数据缓存区域
  255. * burst_length bit数
  256. ********************************************************************************/
  257. void SpiDmaRead(UINT32 *buf , UINT32 burst_length )
  258. {
  259. }
  260. /*******************************************************************************
  261. *正常
  262. * SpiDmaWrite 能正常写
  263. *
  264. * 参数 *buf 数据缓存区域
  265. * burst_length 数据bit数
  266. ********************************************************************************/
  267. void SpiDmaWrite(UINT32 *buf , UINT32 burst_length )
  268. {
  269. }
  270. #endif
  271. static void SpiReadJedecId(UINT8 *mfid, UINT8 *memid, UINT8 *capid)
  272. {
  273. UINT8 val[4];
  274. int i;
  275. SetSpiDataMode(8);
  276. rSPI_DR = SPI_READ_JEDEC_ID;
  277. rSPI_DR = 0;
  278. rSPI_DR = 0;
  279. rSPI_DR = 0;
  280. for (i = 0; i < 4; i++)
  281. {
  282. while(!(rSPI_SR & SPI_RXFIFO_NOTEMPTY));
  283. val[i] = rSPI_DR;
  284. }
  285. *mfid = val[1];
  286. *memid = val[2];
  287. *capid = val[3];
  288. SetSpiDataMode(32);
  289. }
  290. void Test()
  291. {
  292. UINT32 val;
  293. UINT32 i=3;
  294. SpiEmptyRxFIFO();
  295. rSPI_DR = (0xef)<<24;
  296. while(!(rSPI_SR & SPI_RXFIFO_NOTEMPTY));
  297. val = rSPI_DR;
  298. while((rSPI_SR & SPIFLASH_BUSY));
  299. printk("+++++val_t0++++++= 0x%x\n",val);
  300. SpiEmptyRxFIFO();
  301. rSPI_DR = (0xDf)<<24;
  302. while(!(rSPI_SR & SPI_RXFIFO_NOTEMPTY));
  303. val = rSPI_DR;
  304. while((rSPI_SR & SPIFLASH_BUSY));
  305. printk("+++++val_t1++++++= 0x%x\n",val);
  306. SpiEmptyRxFIFO();
  307. rSPI_DR = (0x9f)<<24;
  308. while(!(rSPI_SR & SPI_RXFIFO_NOTEMPTY));
  309. val = rSPI_DR;
  310. while((rSPI_SR & SPIFLASH_BUSY));
  311. printk("+++++val_t2++++++= 0x%x\n",val);
  312. }
  313. static void SpiReadId(void)
  314. {
  315. UINT8 mfid,devid,memid,capid;
  316. SpiReadDeviceId(&mfid,&devid);
  317. SpiReadJedecId(&mfid,&memid,&capid);
  318. PrintVariableValueHex("ManufacturerID: ", mfid);
  319. PrintVariableValueHex("DeviceID: ", devid);
  320. PrintVariableValueHex("Memory Type ID: ", memid);
  321. PrintVariableValueHex("Capacity ID: ", capid);
  322. }
  323. void SpiWritePage(UINT32 pagenum, UINT32 *buf)
  324. {
  325. UINT32 addr;
  326. UINT32 val;
  327. INT32 i;
  328. UINT32 dmach;
  329. UINT8 tmpaddr[3];
  330. addr = pagenum*BYTESPERPAGE;
  331. tmpaddr[0] = addr;
  332. tmpaddr[1] = addr>>8;
  333. tmpaddr[2] = addr>>16;
  334. SpiWriteEnable();
  335. // rSPI_DR = (tmpaddr[0]<<0) | (tmpaddr[1]<<8) | (tmpaddr[2]<<16) | (SPI_PAGE_PROGRAM<<24);
  336. #if 1
  337. #ifdef LITTLE_ENDIAN
  338. rSPI_DR = (tmpaddr[0]<<24) | (tmpaddr[1]<<16) | (tmpaddr[2]<<8) | SPI_PAGE_PROGRAM;
  339. #else
  340. rSPI_DR = (tmpaddr[0]<<0) | (tmpaddr[1]<<8) | (tmpaddr[2]<<16) | (SPI_PAGE_PROGRAM<<24);
  341. #endif
  342. for(i=0;i<WORDSPERPAGE;i++)
  343. {
  344. while(!(rSPI_SR & SPI_TXFIFO_NOTFULL));
  345. rSPI_DR = *buf++;
  346. }
  347. #else
  348. SpiDmaWrite(buf,WORDSPERPAGE);
  349. #endif
  350. while(SpiReadSta() & SPIFLASH_BUSY);
  351. }
  352. /*
  353. void Spi4byteaddrWritePage(UINT32 pagenum, UINT32 *buf)
  354. {
  355. UINT32 addr;
  356. UINT32 val;
  357. INT32 i;
  358. UINT32 dmach;
  359. UINT8 tmpaddr[3];
  360. addr = pagenum*BYTESPERPAGE;
  361. tmpaddr[0] = addr;
  362. tmpaddr[1] = addr>>8;
  363. tmpaddr[2] = addr>>16;
  364. SpiWriteEnable();
  365. rSPI_DR = (tmpaddr[0]<<0) | (tmpaddr[1]<<8) | (tmpaddr[2]<<16) | (SPI_PAGE_PROGRAM<<24);
  366. for(i=0;i<WORDSPERPAGE;i++)
  367. rSPI_DR = *buf++;
  368. while(SpiReadSta() & SPIFLASH_BUSY);
  369. }
  370. */
  371. void SpiReadPage(UINT32 pagenum, UINT32 *buf)
  372. {
  373. UINT32 addr;
  374. UINT32 val;
  375. INT32 i;
  376. UINT32 dmach;
  377. UINT8 tmpaddr[3];
  378. addr = pagenum*BYTESPERPAGE;
  379. tmpaddr[0] = addr;
  380. tmpaddr[1] = addr>>8;
  381. tmpaddr[2] = addr>>16;
  382. SpiEmptyRxFIFO();
  383. /* rSPI_DR = (tmpaddr[0]<<0) | (tmpaddr[1]<<8) | (tmpaddr[2]<<16) | (SPI_READ_DATA<<24);
  384. for(i=0;i<WORDSPERPAGE;i++)
  385. {
  386. rSPI_DR = 0;
  387. }
  388. while(!(rSPI_SR & SPI_RXFIFO_NOTEMPTY));
  389. val = rSPI_DR;
  390. */
  391. #if 1
  392. #ifdef LITTLE_ENDIAN
  393. rSPI_DR = (tmpaddr[0]<<24) | (tmpaddr[1]<<16) | (tmpaddr[2]<<8) | SPI_READ_DATA;
  394. #else
  395. rSPI_DR = (tmpaddr[0]<<0) | (tmpaddr[1]<<8) | (tmpaddr[2]<<16) | (SPI_READ_DATA<<24);
  396. #endif
  397. for(i=0;i<WORDSPERPAGE;i++)
  398. {
  399. while(!(rSPI_SR & SPI_TXFIFO_NOTFULL));
  400. rSPI_DR = 0;
  401. }
  402. while(!(rSPI_SR & SPI_RXFIFO_NOTEMPTY));
  403. val = rSPI_DR;
  404. for(i=0;i<WORDSPERPAGE;i++)
  405. {
  406. while(!(rSPI_SR & SPI_RXFIFO_NOTEMPTY));
  407. *buf++ = rSPI_DR;
  408. }
  409. #else
  410. SpiDmaRead(buf,WORDSPERPAGE);
  411. #endif
  412. }
  413. static void Spi_Read_Sector(UINT32 secnum, UINT32 *buf)
  414. {
  415. INT32 i;
  416. UINT32 basepage;
  417. basepage = secnum*PAGESPERSECTORS;
  418. for(i=0;i<PAGESPERSECTORS;i++)
  419. SpiReadPage(basepage+i,buf+i*WORDSPERPAGE);
  420. }
  421. static void Spi_Write_Sector(UINT32 secnum, UINT32 *buf)
  422. {
  423. INT32 i;
  424. UINT32 basepage;
  425. Spi_SectorErase(secnum);
  426. basepage = secnum*PAGESPERSECTORS;
  427. for(i=0;i<PAGESPERSECTORS;i++)
  428. SpiWritePage(basepage+i,buf+i*WORDSPERPAGE);
  429. }
  430. //待定 SpiReadSingleByte
  431. static UINT8 SpiReadSingleByte(UINT32 addr)
  432. {
  433. UINT32 data;
  434. UINT8 tmpaddr[3];
  435. UINT32 val;
  436. tmpaddr[0] = addr;
  437. tmpaddr[1] = addr>>8;
  438. tmpaddr[2] = addr>>16;
  439. SpiEmptyRxFIFO();
  440. rSPI_DR = (tmpaddr[0]<<0) | (tmpaddr[1]<<8) | (tmpaddr[2]<<16) | (SPI_READ_DATA<<24);
  441. rSPI_DR = 0;
  442. while(!(rSPI_SR & SPI_RXFIFO_NOTEMPTY));
  443. data = rSPI_DR;
  444. while(!(rSPI_SR & SPI_RXFIFO_NOTEMPTY));
  445. data = rSPI_DR;
  446. printk("+++++data = 0x%x++++++\n",data);
  447. return (data&0xFF);
  448. }
  449. #if 0
  450. void SpiFastReadPage(UINT32 pagenum, UINT32 *buf)
  451. {
  452. UINT32 addr;
  453. UINT32 val;
  454. INT32 i;
  455. UINT32 dmach;
  456. UINT8 tmpaddr[3];
  457. UINT8 tmp[64*4+4];
  458. UINT8 *p =(UINT8 *)buf;
  459. addr = pagenum*BYTESPERPAGE;
  460. tmpaddr[0] = addr;
  461. tmpaddr[1] = addr>>8;
  462. tmpaddr[2] = addr>>16;
  463. SpiEmptyRxFIFO();
  464. #if 1
  465. // SpiSetFrameFormatMode(STANDARDFORMAT,READ_ONLY);
  466. rSPI_DR = (tmpaddr[0]<<0) | (tmpaddr[1]<<8) | (tmpaddr[2]<<16) | (SPI_FAST_READ<<24);
  467. #else
  468. SetSpiDataMode(16);
  469. rSPI_DR =SPI_FAST_READ;
  470. rSPI_DR =tmpaddr[2];
  471. rSPI_DR =tmpaddr[1];
  472. rSPI_DR =tmpaddr[0];
  473. rSPI_DR =0;
  474. SetSpiDataMode(32);
  475. #endif
  476. for(i=0;i<WORDSPERPAGE;i++)
  477. {
  478. rSPI_DR = 0;
  479. }
  480. while(!(rSPI_SR & SPI_RXFIFO_NOTEMPTY));
  481. val = rSPI_DR;
  482. for(i=0;i<WORDSPERPAGE;i++)
  483. {
  484. while(!(rSPI_SR & SPI_RXFIFO_NOTEMPTY));
  485. *buf++= rSPI_DR;
  486. }
  487. // for(i= 0;i<WORDSPERPAGE*4;i++)
  488. // (
  489. // p[i] = tmp[i+3];
  490. // )
  491. // SpiSetFrameFormatMode(STANDARDFORMAT,READ_WRITE);
  492. }
  493. #else
  494. void SpiFastReadPage(UINT32 pagenum, UINT32 *buf)
  495. {
  496. UINT32 addr;
  497. UINT32 val;
  498. INT32 i;
  499. UINT32 dmach;
  500. UINT8 tmpaddr[3];
  501. //UINT8 tmp[64*4+4];
  502. UINT32 tmp[65];
  503. UINT8 *p = (UINT8 *)tmp;
  504. UINT8 *q = (UINT8 *)buf;
  505. addr = pagenum*BYTESPERPAGE;
  506. tmpaddr[0] = addr;
  507. tmpaddr[1] = addr>>8;
  508. tmpaddr[2] = addr>>16;
  509. SpiEmptyRxFIFO();
  510. #if 1
  511. // SpiSetFrameFormatMode(STANDARDFORMAT,READ_ONLY);
  512. rSPI_DR = (tmpaddr[0]<<0) | (tmpaddr[1]<<8) | (tmpaddr[2]<<16) | (SPI_FAST_READ<<24);
  513. #else
  514. SetSpiDataMode(8);
  515. rSPI_DR =SPI_FAST_READ;
  516. rSPI_DR =tmpaddr[2];
  517. rSPI_DR =tmpaddr[1];
  518. rSPI_DR =tmpaddr[0];
  519. rSPI_DR =0;
  520. SetSpiDataMode(32);
  521. #endif
  522. for(i=0;i<WORDSPERPAGE+1;i++)
  523. {
  524. rSPI_DR = 0;
  525. }
  526. while(!(rSPI_SR & SPI_RXFIFO_NOTEMPTY));
  527. val = rSPI_DR;
  528. for(i=0;i<WORDSPERPAGE+1;i++)
  529. {
  530. while(!(rSPI_SR & SPI_RXFIFO_NOTEMPTY));
  531. //*buf++= rSPI_DR;
  532. tmp[i]= rSPI_DR;
  533. }
  534. for(i=0;i<WORDSPERPAGE*4;)
  535. {
  536. q[i] = p[i+7];
  537. q[i+1] = p[i];
  538. q[i+2] = p[i+1];
  539. q[i+3] = p[i+2];
  540. i = i+4;
  541. }
  542. // SpiSetFrameFormatMode(STANDARDFORMAT,READ_WRITE);
  543. }
  544. #endif
  545. //********format*********
  546. //00 – Standard SPI Format
  547. // 01 – Dual SPI Format
  548. // 10 – Quad SPI Format
  549. // 11 – Reserved
  550. //********tmod**********
  551. //00 –- Transmit & Receive
  552. //01 –- Transmit Only
  553. //10 –- Receive Only
  554. //11 –- EEPROM Read
  555. void SpiSetFrameFormatMode(unsigned char format,unsigned char tmod)
  556. {
  557. unsigned int val = 0;
  558. while((rSPI_SR & SPI_BUSY));
  559. rSPI_SSIENR = 0;
  560. val = rSPI_CTLR0;
  561. val &=~((0x3<<21)|(0x3<<8));
  562. val |=((format<<21)|(tmod<<8));
  563. rSPI_CTLR0 = val;
  564. rSPI_SSIENR = 1;
  565. }
  566. void Spi4bitModeReadPgae(UINT32 pagenum, UINT32 *buf)
  567. {
  568. UINT32 addr;
  569. UINT32 val;
  570. INT32 i;
  571. UINT32 dmach;
  572. UINT8 tmpaddr[3];
  573. addr = pagenum*BYTESPERPAGE;
  574. tmpaddr[0] = addr;
  575. tmpaddr[1] = addr>>8;
  576. tmpaddr[2] = addr>>16;
  577. SpiEmptyRxFIFO();
  578. SetCSGpioEnable(1);
  579. SpiSetFrameFormatMode(QUADFORMAT, READ_ONLY);
  580. //set instruction 8bits,1byte mode; addr 24bit,1byte mode; 8 dummy clocks
  581. rSPI_SSIENR = 0;
  582. rSPI_SPI_CTRLR0 = (8 << 11) | (2 << 8) | (6 << 2);
  583. rSPI_SSIENR = 1;
  584. SetSpiDataMode(32);
  585. SetSpiRevNDF(WORDSPERPAGE - 1);
  586. rSPI_DR = SPI_4READ_MODE1;
  587. rSPI_DR = addr;//(tmpaddr[2] << 8) | (tmpaddr[1] << 16) | (tmpaddr[0] << 24);
  588. for(i=0; i<WORDSPERPAGE; i++)
  589. {
  590. while(!(rSPI_SR & SPI_RXFIFO_NOTEMPTY));
  591. *buf++ = rSPI_DR;
  592. }
  593. SpiSetFrameFormatMode(STANDARDFORMAT, READ_WRITE);
  594. while((rSPI_SR & SPI_BUSY));
  595. SetCSGpioEnable(0);
  596. }
  597. void Spi4bitModeReadPgae_4byte(UINT32 pagenum, UINT32 *buf)
  598. {
  599. UINT32 addr;
  600. UINT32 val;
  601. INT32 i;
  602. UINT32 dmach;
  603. UINT8 tmpaddr[4];
  604. addr = pagenum*BYTESPERPAGE;
  605. tmpaddr[0] = addr;
  606. tmpaddr[1] = addr>>8;
  607. tmpaddr[2] = addr>>16;
  608. tmpaddr[3] = addr>>24;
  609. SpiEmptyRxFIFO();
  610. rSPI_SSIENR = 0;
  611. rSPI_SPI_CTRLR0 = (0x6<<11)|(0x2<<8)|(0x8<<2)|(0x1<<0);
  612. rSPI_SSIENR = 1;
  613. SpiSetFrameFormatMode(QUADFORMAT,READ_ONLY);
  614. // SetCSGpioOutData(0);
  615. // rSPI_DR = (tmpaddr[0]<<0) | (tmpaddr[1]<<8) | (tmpaddr[2]<<16) | (SPI_4READ_MODE1<<24);
  616. rSPI_DR = 0xec;//SPI_4READ_MODE1;
  617. rSPI_DR = (tmpaddr[0]<<0) | (tmpaddr[1]<<8) | (tmpaddr[2]<<16)|(tmpaddr[2]<<24);
  618. for(i=0;i<WORDSPERPAGE;i++)
  619. {
  620. rSPI_DR = 0;
  621. }
  622. while(!(rSPI_SR & SPI_RXFIFO_NOTEMPTY));
  623. // val = rSPI_DR;
  624. for(i=0;i<WORDSPERPAGE;i++)
  625. {
  626. while(!(rSPI_SR & SPI_RXFIFO_NOTEMPTY));
  627. *buf++ = rSPI_DR;
  628. }
  629. // SetCSGpioOutData(1);
  630. SpiSetFrameFormatMode(STANDARDFORMAT,READ_WRITE);
  631. }
  632. void Spi4bitModeWritePage(UINT32 pagenum, UINT32 *buf)
  633. {
  634. UINT32 addr;
  635. UINT32 val;
  636. INT32 i;
  637. UINT32 dmach;
  638. UINT8 tmpaddr[3];
  639. addr = pagenum*BYTESPERPAGE;
  640. tmpaddr[0] = addr;
  641. tmpaddr[1] = addr>>8;
  642. tmpaddr[2] = addr>>16;
  643. SpiWriteEnable();
  644. SpiEmptyRxFIFO();
  645. SetCSGpioEnable(1);
  646. SpiSetFrameFormatMode(QUADFORMAT, WRITE_ONLY);
  647. //set instruction 8bits,1byte mode; addr 24bit,1byte mode; no dummy clocks
  648. rSPI_SSIENR = 0;
  649. rSPI_SPI_CTRLR0 = (2 << 8) | (6 << 2);
  650. rSPI_SSIENR = 1;
  651. SetSpiDataMode(32);
  652. rSPI_DR = SPI_4WRITE_MODE;
  653. rSPI_DR = addr;//(tmpaddr[2] << 8) | (tmpaddr[1] << 16) | (tmpaddr[0] << 24);
  654. for(i=0; i<WORDSPERPAGE; i++)
  655. {
  656. while(!(rSPI_SR & SPI_TXFIFO_NOTFULL));
  657. rSPI_DR = *buf++;
  658. }
  659. SpiSetFrameFormatMode(STANDARDFORMAT, READ_WRITE);
  660. SetCSGpioEnable(0);
  661. delay(100);
  662. SetCSGpioEnable(1);
  663. while(SpiReadSta() & SPIFLASH_BUSY);
  664. SetCSGpioEnable(0);
  665. }
  666. void SpiEraseBlock(UINT32 blockNum)
  667. {
  668. UINT32 addr;
  669. UINT8 tmpaddr[3];
  670. addr = BYTESPERBLOCK*blockNum;
  671. tmpaddr[0] = addr;
  672. tmpaddr[1] = addr>>8;
  673. tmpaddr[2] = addr>>16;
  674. printk("\nStart erase the spi flash block %d,\n",blockNum);
  675. SpiWriteEnable();
  676. #ifdef LITTLE_ENDIAN
  677. rSPI_DR = (tmpaddr[0]<<24) | (tmpaddr[1]<<16) | (tmpaddr[2]<<8) | SPI_BLOCK_ERASE;
  678. #else
  679. rSPI_DR = (tmpaddr[0]<<0) | (tmpaddr[1]<<8) | (tmpaddr[2]<<16) | SPI_BLOCK_ERASE<<24;
  680. #endif
  681. while((SpiReadSta() & SPIFLASH_WRITEENABLE));
  682. printk("\nThe block erased!\n");
  683. }
  684. void SpiEraseChip(void)
  685. {
  686. UINT32 i;
  687. printk("\nStart erase the whole spi flash,please wait...\n");
  688. SpiWriteEnable();
  689. SetSpiDataMode(8);
  690. rSPI_DR = SPI_CHIP_ERASE;
  691. SetSpiDataMode(32);
  692. while(SpiReadSta() & SPIFLASH_BUSY);
  693. printk("\n The whole flash erased! \n");
  694. }
  695. //UINT32 WriteData[WORDSPERPAGE];
  696. //UINT32 ReadData[WORDSPERPAGE];
  697. UINT8 WriteData[WORDSPERPAGE*4];
  698. UINT8 ReadData[WORDSPERPAGE*4];
  699. void TestSpiRWPage(void)
  700. {
  701. INT32 i,j,k,p,m;
  702. UINT32 page = 0;
  703. UINT8 data = 0;
  704. // SpiEraseChip();
  705. SpiEraseBlock(0);
  706. for(i = 0;i<64*4;i++)
  707. {
  708. WriteData[i] = 0x5a505000+i;
  709. ReadData[i] = 0;
  710. }
  711. for(j = 0;j<64;j++)
  712. {
  713. SpiEraseBlock(j);
  714. for(k=0;k<16;k++)
  715. {
  716. for(m=0;m<16;m++)
  717. {
  718. page = j*16*16+k*16+m;
  719. printk("Test the Page %d \n",page);
  720. SpiWritePage(page,(UINT32 *)WriteData);
  721. SpiReadPage(page,(UINT32 *)ReadData);
  722. //SpiFastReadPage(page,(UINT32 *)ReadData);
  723. // data = SpiReadSingleByte(0);
  724. for(i = 0;i<WORDSPERPAGE*4;i++)
  725. if(ReadData[i]!=WriteData[i])
  726. {
  727. printk("SPI Read or Write error ReadData[%d]=0x%x,WriteData[%d]=0x%x\n",i,ReadData[i],i,WriteData[i]);
  728. //break;
  729. }
  730. }
  731. }
  732. }
  733. }
  734. void Spi_QE_enable(unsigned char flag)
  735. {
  736. UINT8 status = 0;
  737. status = SpiReadSta2();
  738. if(flag)
  739. {
  740. status &= ~(1<<1);
  741. status |= (1<<1);
  742. }
  743. else
  744. status &= ~(1<<1);
  745. SpiWriteSta2(status);
  746. }
  747. /*void Spi4Byte(int enable)
  748. {
  749. printk("\nSpi enable 4 byte address mode.\n");
  750. SetSpiDataMode(8);
  751. if(enable)
  752. rSPI_DR = SPI_WINBOND_4BYTE;
  753. else
  754. rSPI_DR = SPI_WINBOND_3BYTE;
  755. SetSpiDataMode(32);
  756. while((SpiReadSta() & SPIFLASH_BUSY));
  757. }
  758. */
  759. void Test4bitMode(void)
  760. {
  761. unsigned int i=0;
  762. //SpiEraseChip();
  763. SpiEraseBlock(0);
  764. for(i = 0;i<64*4;i++)
  765. {
  766. ReadData[i] = 0;
  767. }
  768. SpiReadPage(0,(UINT32 *)ReadData);
  769. for(i = 0;i<64*4;i++)
  770. {
  771. WriteData[i] = 0x10+i;
  772. ReadData[i] = 0;
  773. }
  774. Spi_QE_enable(1);
  775. Spi4bitModeWritePage(0,(UINT32 *)WriteData);
  776. //SpiWritePage(0,(UINT32 *)WriteData);
  777. //SpiReadPage(0,(UINT32 *)ReadData);
  778. Spi4bitModeReadPgae(0,(UINT32 *)ReadData);
  779. //Spi4Byte(1);
  780. //Spi4bitModeReadPgae_4byte(0,(UINT32 *)ReadData);
  781. for(i= 0;i<64*4;i++)
  782. if(ReadData[i]!=WriteData[i])
  783. printk("Write or Read page 0 error %d!!!!\n",i);
  784. }
  785. /* SPI NAND commands */
  786. #define SPI_NAND_WRITE_ENABLE 0x06
  787. #define SPI_NAND_WRITE_DISABLE 0x04
  788. #define SPI_NAND_GET_FEATURE 0x0f
  789. #define SPI_NAND_SET_FEATURE 0x1f
  790. #define SPI_NAND_PAGE_READ 0x13
  791. #define SPI_NAND_READ_CACHE 0x03
  792. #define SPI_NAND_FAST_READ_CACHE 0x0b
  793. #define SPI_NAND_READ_CACHE_X2 0x3b
  794. #define SPI_NAND_READ_CACHE_X4 0x6b
  795. #define SPI_NAND_READ_CACHE_DUAL_IO 0xbb
  796. #define SPI_NAND_READ_CACHE_QUAD_IO 0xeb
  797. #define SPI_NAND_READ_ID 0x9f
  798. #define SPI_NAND_PROGRAM_LOAD 0x02
  799. #define SPI_NAND_PROGRAM_LOAD4 0x32
  800. #define SPI_NAND_PROGRAM_EXEC 0x10
  801. #define SPI_NAND_PROGRAM_LOAD_RANDOM 0x84
  802. #define SPI_NAND_PROGRAM_LOAD_RANDOM4 0xc4
  803. #define SPI_NAND_BLOCK_ERASE 0xd8
  804. #define SPI_NAND_RESET 0xff
  805. /* Registers common to all devices */
  806. #define SPI_NAND_LOCK_REG 0xa0
  807. #define SPI_NAND_PROT_UNLOCK_ALL 0x0
  808. #define SPI_NAND_FEATURE_REG 0xb0
  809. #define SPI_NAND_ECC_EN (1 << 4)
  810. #define SPI_NAND_QUAD_EN (1 << 0)
  811. #define SPI_NAND_STATUS_REG 0xc0
  812. #define SPI_NAND_STATUS_REG_ECC_MASK 0x3
  813. #define SPI_NAND_STATUS_REG_ECC_SHIFT 4
  814. #define SPI_NAND_STATUS_REG_PROG_FAIL (1 << 3)
  815. #define SPI_NAND_STATUS_REG_ERASE_FAIL (1 << 2)
  816. #define SPI_NAND_STATUS_REG_WREN (1 << 1)
  817. #define SPI_NAND_STATUS_REG_BUSY (1 << 0)
  818. #define SPI_NAND_ECC_UNCORR 0x2
  819. #define PAGES_PER_BLOCK 64
  820. #define BYTES_PER_PAGE 2048
  821. static void SpinandSoftreset(void)
  822. {
  823. SetSpiDataMode(8);
  824. SetCSGpioEnable(1);
  825. rSPI_DR = SPI_NAND_RESET;
  826. while((rSPI_SR & SPI_BUSY));
  827. SetCSGpioEnable(0);
  828. SetSpiDataMode(32);
  829. }
  830. static void SpiNandReadId(void)
  831. {
  832. UINT8 val[4];
  833. UINT8 mfid, devid;
  834. int i;
  835. SetSpiDataMode(8);
  836. SetCSGpioEnable(1);
  837. rSPI_DR = SPI_NAND_READ_ID;
  838. rSPI_DR = 0;
  839. rSPI_DR = 0;
  840. rSPI_DR = 0;
  841. for(i = 0; i < 4; i++)
  842. {
  843. while(!(rSPI_SR & SPI_RXFIFO_NOTEMPTY));
  844. val[i] = rSPI_DR;
  845. }
  846. while((rSPI_SR & SPI_BUSY));
  847. SetCSGpioEnable(0);
  848. SetSpiDataMode(32);
  849. PrintVariableValueHex("ManufacturerID0: ", val[1]);
  850. PrintVariableValueHex("ManufacturerID: ", val[2]);
  851. PrintVariableValueHex("DeviceID: ", val[3]);
  852. }
  853. static void SpiNandWriteReg(u8 opcode, u8 val)
  854. {
  855. SetSpiDataMode(8);
  856. SetCSGpioEnable(1);
  857. rSPI_DR = SPI_NAND_SET_FEATURE;
  858. rSPI_DR = opcode;
  859. rSPI_DR = val;
  860. while((rSPI_SR & SPI_BUSY));
  861. SetCSGpioEnable(0);
  862. SetSpiDataMode(32);
  863. }
  864. static u8 SpiNandReadReg(u8 opcode)
  865. {
  866. u8 val;
  867. int i;
  868. SetSpiDataMode(8);
  869. SetCSGpioEnable(1);
  870. rSPI_DR = SPI_NAND_GET_FEATURE;
  871. rSPI_DR = opcode;
  872. rSPI_DR = 0;
  873. for (i = 0; i < 3; i++)
  874. {
  875. while(!(rSPI_SR & SPI_RXFIFO_NOTEMPTY));
  876. val = rSPI_DR;
  877. }
  878. while((rSPI_SR & SPI_BUSY));
  879. SetCSGpioEnable(0);
  880. SetSpiDataMode(32);
  881. return val;
  882. }
  883. void SpiNandWriteEnable(void)
  884. {
  885. SetSpiDataMode(8);
  886. SetCSGpioEnable(1);
  887. rSPI_DR = SPI_NAND_WRITE_ENABLE;
  888. while((rSPI_SR & SPI_BUSY));
  889. SetCSGpioEnable(0);
  890. SetSpiDataMode(32);
  891. }
  892. void SpiNandEraseBlock(int blknum)
  893. {
  894. UINT32 page_addr = blknum * PAGES_PER_BLOCK;
  895. SetSpiDataMode(8);
  896. SetCSGpioEnable(1);
  897. rSPI_DR = SPI_NAND_BLOCK_ERASE;
  898. rSPI_DR = (page_addr >> 16) & 0xff;
  899. rSPI_DR = (page_addr >> 8) & 0xff;
  900. rSPI_DR = page_addr & 0xff;
  901. while((rSPI_SR & SPI_BUSY));
  902. SetCSGpioEnable(0);
  903. SetSpiDataMode(32);
  904. }
  905. int SpiNandWaitTillReady(void)
  906. {
  907. int timeout = 100;
  908. u8 status;
  909. while(timeout--)
  910. {
  911. status = SpiNandReadReg(SPI_NAND_STATUS_REG);
  912. //printk("status=0x%x.\n", status);
  913. if (!(status & SPI_NAND_STATUS_REG_BUSY))
  914. return status;
  915. delay(1000);
  916. }
  917. return -1;
  918. }
  919. static int SpiNandEnableECC(void)
  920. {
  921. u8 status;
  922. status = SpiNandReadReg(SPI_NAND_FEATURE_REG);
  923. status |= SPI_NAND_ECC_EN;
  924. SpiNandWriteReg(SPI_NAND_FEATURE_REG, status);
  925. return 0;
  926. }
  927. static int SpiNandDisableQuad(void)
  928. {
  929. u8 status;
  930. status = SpiNandReadReg(SPI_NAND_FEATURE_REG);
  931. status &= ~SPI_NAND_QUAD_EN;
  932. SpiNandWriteReg(SPI_NAND_FEATURE_REG, status);
  933. return 0;
  934. }
  935. void SpiNandLoadPage(unsigned int page_addr)
  936. {
  937. SetSpiDataMode(8);
  938. SetCSGpioEnable(1);
  939. rSPI_DR = SPI_NAND_PAGE_READ;
  940. rSPI_DR = (page_addr >> 16) & 0xff;
  941. rSPI_DR = (page_addr >> 8) & 0xff;
  942. rSPI_DR = page_addr & 0xff;
  943. while((rSPI_SR & SPI_BUSY));
  944. SetCSGpioEnable(0);
  945. SetSpiDataMode(32);
  946. }
  947. void SpiNandStorePage(unsigned int page_addr)
  948. {
  949. SetSpiDataMode(8);
  950. SetCSGpioEnable(1);
  951. rSPI_DR = SPI_NAND_PROGRAM_EXEC;
  952. rSPI_DR = (page_addr >> 16) & 0xff;
  953. rSPI_DR = (page_addr >> 8) & 0xff;
  954. rSPI_DR = page_addr & 0xff;
  955. while((rSPI_SR & SPI_BUSY));
  956. SetCSGpioEnable(0);
  957. SetSpiDataMode(32);
  958. }
  959. int SpiNandReadCache(unsigned int page_offset, int length, u8 *read_buf)
  960. {
  961. int i;
  962. u8 val;
  963. SetSpiDataMode(8);
  964. SetCSGpioEnable(1);
  965. rSPI_DR = SPI_NAND_READ_CACHE;
  966. rSPI_DR = (page_offset >> 8) & 0xff;
  967. rSPI_DR = page_offset & 0xff;
  968. rSPI_DR = 0;
  969. for (i = 0; i < 4; i++)
  970. {
  971. while(!(rSPI_SR & SPI_RXFIFO_NOTEMPTY));
  972. val = rSPI_DR;
  973. }
  974. for (i = 0; i < length; i++)
  975. {
  976. rSPI_DR = 0;
  977. while(!(rSPI_SR & SPI_RXFIFO_NOTEMPTY));
  978. read_buf[i] = rSPI_DR;
  979. }
  980. while((rSPI_SR & SPI_BUSY));
  981. SetCSGpioEnable(0);
  982. SetSpiDataMode(32);
  983. }
  984. int SpiNandReadPage(unsigned int page_addr, void *buf)
  985. {
  986. int status;
  987. int ecc_status;
  988. SpiNandLoadPage(page_addr);
  989. status = SpiNandWaitTillReady();
  990. if (status < 0)
  991. return status;
  992. ecc_status = (status >> SPI_NAND_STATUS_REG_ECC_SHIFT) &
  993. SPI_NAND_STATUS_REG_ECC_MASK;
  994. if (ecc_status == SPI_NAND_ECC_UNCORR)
  995. {
  996. printk("Bit errors greater than ECC capability(8 bits) and not corrected.\n");
  997. return -1;
  998. }
  999. SpiNandReadCache(0, BYTES_PER_PAGE, buf);
  1000. }
  1001. int SpiNandStoreCache(unsigned int page_offset, int length, u8 *write_buf)
  1002. {
  1003. int i;
  1004. u8 val;
  1005. SetSpiDataMode(8);
  1006. SetCSGpioEnable(1);
  1007. rSPI_DR = SPI_NAND_PROGRAM_LOAD;
  1008. rSPI_DR = (page_offset >> 8) & 0xff;
  1009. rSPI_DR = page_offset & 0xff;
  1010. for (i = 0; i < length; i++)
  1011. {
  1012. while(!(rSPI_SR & SPI_TXFIFO_NOTFULL));
  1013. rSPI_DR = write_buf[i];
  1014. }
  1015. while((rSPI_SR & SPI_BUSY));
  1016. SetCSGpioEnable(0);
  1017. SetSpiDataMode(32);
  1018. }
  1019. void SpiNandWritePage(unsigned int page_addr, void *buf)
  1020. {
  1021. SpiNandWriteEnable();
  1022. SpiNandStoreCache(0, BYTES_PER_PAGE, buf);
  1023. SpiNandStorePage(page_addr);
  1024. SpiNandWaitTillReady();
  1025. }
  1026. u8 spinand_wbuf[2048];
  1027. u8 spinand_rbuf[2048] = {0};
  1028. #if 0
  1029. void bootFromSPI()
  1030. {
  1031. void (*funPtr)(void);
  1032. INT32 nSectorLen;
  1033. UINT32 *pData;
  1034. INT32 nMaxSectors;
  1035. INT32 nLeftSize;
  1036. INT32 nReadSize;
  1037. INT32 i,j,k,p,m;
  1038. UINT32 addr;
  1039. UINT8 status;
  1040. printk("SPI Booter\n");
  1041. SpiSelectPad();
  1042. #if 0
  1043. SetCSGpioEnable(1);
  1044. rSPI_SSIENR = 0;
  1045. rSPI_CTLR0 = (2 << 21) | (31 << 16) | (1 << 8);
  1046. rSPI_SPI_CTRLR0 = (2 << 8) | (6 << 2);
  1047. //rSPI_CTLR1 = 63;
  1048. rSPI_BAUDR = 4;
  1049. rSPI_SER = 1;
  1050. rSPI_SSIENR = 1;
  1051. rSPI_DR = 0x32;
  1052. rSPI_DR = 0;
  1053. rSPI_DR = 0x12345678;
  1054. rSPI_DR = 0x12345678;
  1055. while(1);
  1056. #endif
  1057. SpiInit();
  1058. SpinandSoftreset();
  1059. SpiNandWaitTillReady();
  1060. SpiNandReadId();
  1061. SpiNandWriteReg(SPI_NAND_LOCK_REG, SPI_NAND_PROT_UNLOCK_ALL);
  1062. SpiNandEnableECC();
  1063. SpiNandDisableQuad();
  1064. SpiNandWriteEnable();
  1065. SpiNandEraseBlock(0);
  1066. SpiNandWaitTillReady();
  1067. #if 0
  1068. for (i = 0; i < BYTES_PER_PAGE; i++)
  1069. spinand_wbuf[i] = rand();
  1070. SpiNandWritePage(0, spinand_wbuf);
  1071. SpiNandReadPage(0, spinand_rbuf);
  1072. for (i = 0; i < BYTES_PER_PAGE; i++)
  1073. {
  1074. if (spinand_wbuf[i] != spinand_rbuf[i])
  1075. printk("compare data fail 0x%.2x 0x%.2x.\n", spinand_wbuf[i], spinand_rbuf[i]);
  1076. }
  1077. #else
  1078. pData = (UINT32*)0x42000000;
  1079. for (i = 0; i < 8; i++)
  1080. {
  1081. SpiNandWritePage(i, pData);
  1082. pData += BYTES_PER_PAGE / 4;
  1083. }
  1084. SpiNandReadPage(0, (void*)0x43000000);
  1085. #endif
  1086. while(1);
  1087. #if 1
  1088. // TestSpiInterrupt();
  1089. // TestSpiRWPage();
  1090. // TestFastRead();
  1091. Test4bitMode();
  1092. #else //test the QE enable
  1093. status = SpiReadSta();
  1094. status &= ~(1<<6);
  1095. status |= (1<<6);
  1096. SpiWriteSta(status);
  1097. status = SpiReadSta();
  1098. printk("+++00+++status = 0x%x++++\n",status);
  1099. SpiWriteDisable();
  1100. status = SpiReadSta();
  1101. printk("+++01+++status = 0x%x++++\n",status);
  1102. #endif
  1103. printk("Test Over!!!\n");
  1104. while(1);
  1105. }
  1106. #endif
  1107. static void BurnSpiNandData(unsigned int Memaddr, unsigned int addr, unsigned int size)
  1108. {
  1109. INT32 i;
  1110. INT32 nStartPage;
  1111. UINT8 *pDataBuf;
  1112. INT32 nPages;
  1113. pDataBuf = (UINT8*)Memaddr;
  1114. PrintVariableValueHex("memaddr Address ", Memaddr);
  1115. PrintVariableValueHex("Spi Address ", addr);
  1116. PrintVariableValueHex("Write size ", size);
  1117. nStartPage = addr / BYTES_PER_PAGE;
  1118. nPages = (size + BYTES_PER_PAGE - 1) / BYTES_PER_PAGE;
  1119. for(i = nStartPage; i < nStartPage + nPages; i++)
  1120. {
  1121. SpiNandWritePage(i,(UINT32 *)pDataBuf);
  1122. pDataBuf += BYTES_PER_PAGE;
  1123. printf("#");
  1124. }
  1125. }
  1126. void SpiNandBurnLoad(void)
  1127. {
  1128. void (*funPtr)(void);
  1129. UINT8 *pData;
  1130. INT32 i,j;
  1131. INT32 nPageCount;
  1132. u8 *spinand_wbuf = (UINT8 *)(0x30A000);
  1133. u8 *spinand_rbuf = (UINT8 *)(0x30C000);
  1134. u8 *spinand_tbuf = (UINT8 *)(0x30A000);
  1135. SpiSelectPad();
  1136. SpiInit();
  1137. SpinandSoftreset();
  1138. SpiNandWaitTillReady();
  1139. SpiNandReadId();
  1140. SpiNandWriteReg(SPI_NAND_LOCK_REG, SPI_NAND_PROT_UNLOCK_ALL);
  1141. SpiNandEnableECC();
  1142. SpiNandDisableQuad();
  1143. #if 1
  1144. SpiNandWriteEnable();
  1145. SpiNandEraseBlock(0);
  1146. SpiNandWaitTillReady();
  1147. BurnSpiNandData(0x30A000, 0, 0x4000);
  1148. printf("\r\nBurn the spi Nand Flash Over !!!\n");
  1149. while(1);
  1150. #else
  1151. pData = (UINT8*)IMAGE_ENTRY;
  1152. nPageCount = (IMAGE_MAX_SIZE + BYTES_PER_PAGE - 1) / BYTES_PER_PAGE;
  1153. for(i = 0; i < nPageCount; i++) {
  1154. SpiNandReadPage(i, pData);
  1155. pData += BYTES_PER_PAGE;
  1156. }
  1157. printf("Read the spi Nand Flash Over !!!\n");
  1158. while(1);
  1159. #endif
  1160. #if 1
  1161. SpiNandWriteEnable();
  1162. SpiNandEraseBlock(0);
  1163. SpiNandWaitTillReady();
  1164. /* for (i = 0; i < BYTES_PER_PAGE; i++)
  1165. {
  1166. spinand_wbuf[i] = i;//rand();
  1167. spinand_rbuf[i] = 0;
  1168. }
  1169. */
  1170. for(i = 0;i<8;i++)
  1171. { //i = 23;
  1172. /*
  1173. for (j = 0; j < BYTES_PER_PAGE; j++)
  1174. {
  1175. spinand_wbuf[j] = j;//rand();
  1176. spinand_rbuf[j] = 0;
  1177. }
  1178. */
  1179. printk("test block 0 page i = %d\n",i);
  1180. SpiNandWritePage(i, spinand_wbuf);
  1181. delay(1000);
  1182. #if 0
  1183. SpiNandReadPage(i, spinand_rbuf);
  1184. delay(1000);
  1185. for (j = 0; j < BYTES_PER_PAGE; j++)
  1186. {
  1187. if (spinand_wbuf[j] != spinand_rbuf[j])
  1188. {
  1189. printk("page %d offset %d compare data fail 0x%.2x 0x%.2x.\n", i,j,spinand_wbuf[j], spinand_rbuf[j]);
  1190. //SendUartString("data is error!!!!\n");
  1191. //break;
  1192. }
  1193. }
  1194. #endif
  1195. spinand_wbuf += BYTES_PER_PAGE;
  1196. spinand_rbuf += BYTES_PER_PAGE;
  1197. }
  1198. SendUartString("test data over!!\n");
  1199. while(1);
  1200. pData = (UINT8*)IMAGE_ENTRY;
  1201. nPageCount = (IMAGE_MAX_SIZE + BYTES_PER_PAGE - 1) / BYTES_PER_PAGE;
  1202. for(i = 0; i < nPageCount; i++) {
  1203. SpiNandReadPage(i, pData);
  1204. pData += BYTES_PER_PAGE;
  1205. }
  1206. if (CheckImageValid) {
  1207. funPtr = (void (*)(void))IMAGE_ENTRY;
  1208. funPtr();
  1209. } else
  1210. SendUartString("Can't find loader image\n");
  1211. #endif
  1212. }