更新MCU工程（iram版本和sram-nos版本）

	优化pll配置(调整VCO参数范围为625MHz~2500MHz)，并以此调整AHB和SYS锁相环的分频系数。

amt630hv160-mcu/amt630hv160-mcu-iram/src/ArkmicroFiles/libcpu-amt630hv160/source/amt630hv160_clk.c

@@ -115,7 +115,7 @@ static int CLK_SetSprd(u32 pllcfgreg, u32 sprd_permil, u32 sprd_freq)
 	}
 
 	vco = HSE_Value / REFDIV * FBDIV1;
-	if (vco < 400000000 || vco > 1600000000) {
+	if (vco < 625000000 || vco > 2500000000) {
 		printf("sprd config abnormal(vco overrun).\n");
 		return -1;
 	}
@@ -150,6 +150,8 @@ void CLK_SetFreq(u32 pllcfgreg, u64 freq, u8 ensprd)
 			sprd_permil = SYSPLL_SPRD_PERM;
 			sprd_freq = SYSPLL_SPRD_FREQ;
 			refdiv = 12;
+		} else {
+			postdiv1 = 4;
 		}
 	} else if (pllcfgreg == (u32)&SYSCTRL->AHBPLL_CFG) {
 		SYSCTRL->AHBPLL_SPRD_CTL |= (1 << 30);
@@ -157,6 +159,8 @@ void CLK_SetFreq(u32 pllcfgreg, u64 freq, u8 ensprd)
 			sprd_permil = AHBPLL_SPRD_PERM;
 			sprd_freq = AHBPLL_SPRD_FREQ;
 			refdiv = 12;
+		} else {
+			postdiv1 = 3;
 		}
 	} else if (pllcfgreg == (u32)&SYSCTRL->VPUPLL_CFG) {
 		SYSCTRL->VPUPLL_SPRD_CTL |= (1 << 30);
@@ -180,7 +184,7 @@ void CLK_SetFreq(u32 pllcfgreg, u64 freq, u8 ensprd)
 	}
 
 	vco = HSE_Value / refdiv * fbdiv;
-	if (vco < 400000000 || vco > 1600000000) {
+	if (vco < 625000000 || vco > 2500000000) {
 		printf("clock config abnormal.\n");
 		while(1);
 	}

amt630hv160-mcu/amt630hv160-mcu-sram-nos/src/ArkmicroFiles/libcpu-amt630hv160/source/amt630hv160_clk.c

@@ -115,7 +115,7 @@ static int CLK_SetSprd(u32 pllcfgreg, u32 sprd_permil, u32 sprd_freq)
 	}
 
 	vco = HSE_Value / REFDIV * FBDIV1;
-	if (vco < 400000000 || vco > 1600000000) {
+	if (vco < 625000000 || vco > 2500000000) {
 		printf("sprd config abnormal(vco overrun).\n");
 		return -1;
 	}
@@ -150,6 +150,8 @@ void CLK_SetFreq(u32 pllcfgreg, u64 freq, u8 ensprd)
 			sprd_permil = SYSPLL_SPRD_PERM;
 			sprd_freq = SYSPLL_SPRD_FREQ;
 			refdiv = 12;
+		} else {
+			postdiv1 = 4;
 		}
 	} else if (pllcfgreg == (u32)&SYSCTRL->AHBPLL_CFG) {
 		SYSCTRL->AHBPLL_SPRD_CTL |= (1 << 30);
@@ -157,6 +159,8 @@ void CLK_SetFreq(u32 pllcfgreg, u64 freq, u8 ensprd)
 			sprd_permil = AHBPLL_SPRD_PERM;
 			sprd_freq = AHBPLL_SPRD_FREQ;
 			refdiv = 12;
+		} else {
+			postdiv1 = 3;
 		}
 	} else if (pllcfgreg == (u32)&SYSCTRL->VPUPLL_CFG) {
 		SYSCTRL->VPUPLL_SPRD_CTL |= (1 << 30);
@@ -180,7 +184,7 @@ void CLK_SetFreq(u32 pllcfgreg, u64 freq, u8 ensprd)
 	}
 
 	vco = HSE_Value / refdiv * fbdiv;
-	if (vco < 400000000 || vco > 1600000000) {
+	if (vco < 625000000 || vco > 2500000000) {
 		printf("clock config abnormal.\n");
 		while(1);
 	}