更新CPU工程：

	1.更新ecspi驱动，添加从机模式的逻辑代码，同时使能TR中断并设置相应阈值，以优化数据连续传输过程中出现的收发异常现象。
	2.更新ecspi驱动，调整主机模式下中断触发的rxfifo阈值。
	3.重构wrap驱动代码，优化驱动逻辑。

amt630hv160-freertos-beta/ArkmicroFiles/libcpu-amt630hv160/source/ecspi.c

@@ -6,7 +6,8 @@
 
 #define SPI1_CS0_GPIO		86
 
-#define USE_DMA_THRESHOLD	32
+#define USE_DMA_MIN_THRESHOLD	32
+#define USE_DMA_MAX_THRESHOLD	512
 #define MALLOC_DMA_MEM_SIZE	0x1000
 
 
@@ -14,13 +15,57 @@
 #define ARK_ECSPI_TXDATA	0x460
 
 /* generic defines to abstract from the different register layouts */
-#define ARK_INT_RR	(1 << 0) /* Receive data ready interrupt */
-#define ARK_INT_TE	(1 << 1) /* Transmit FIFO empty interrupt */
+#define ARK_INT_RR (1 << 0) /* Receive data ready interrupt */
+#define ARK_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */
+#define ARK_INT_TC (1 << 2) /* Transfer Completed interrupt */
+#define ARK_INT_TF (1 << 3)
+#define ARK_INT_TR (1 << 4)	/* Transmit FIFO request interrupt */
 
 /* The maximum  bytes that a sdma BD can transfer.*/
 #define MAX_SDMA_BD_BYTES  (1 << 15)
 #define ARK_ECSPI_CTRL_MAX_BURST	512
 
+#define ARK_ECSPI_CTRL		0x08
+#define ARK_ECSPI_CTRL_ENABLE		(1 <<  0)
+#define ARK_ECSPI_CTRL_XCH		(1 <<  2)
+#define ARK_ECSPI_CTRL_SMC		(1 << 3)
+#define ARK_ECSPI_CTRL_MODE_MASK	(0xf << 4)
+#define ARK_ECSPI_CTRL_DRCTL(drctl)	((drctl) << 16)
+#define ARK_ECSPI_CTRL_POSTDIV_OFFSET	8
+#define ARK_ECSPI_CTRL_PREDIV_OFFSET	12
+#define ARK_ECSPI_CTRL_CS(cs)		((cs) << 18)
+#define ARK_ECSPI_CTRL_BL_OFFSET	20
+#define ARK_ECSPI_CTRL_BL_MASK		(0xfff << 20)
+
+#define ARK_ECSPI_CONFIG	0x0c
+#define ARK_ECSPI_CONFIG_SCLKPHA(cs)	(1 << ((cs) +  0))
+#define ARK_ECSPI_CONFIG_SCLKPOL(cs)	(1 << ((cs) +  4))
+#define ARK_ECSPI_CONFIG_SBBCTRL(cs)	(1 << ((cs) +  8))
+#define ARK_ECSPI_CONFIG_SSBPOL(cs)	(1 << ((cs) + 12))
+#define ARK_ECSPI_CONFIG_SCLKCTL(cs)	(1 << ((cs) + 20))
+
+#define ARK_ECSPI_INT 0x10
+#define ARK_ECSPI_INT_TEEN (1 << 0)
+#define ARK_ECSPI_INT_TREN (1 << 1)
+#define ARK_ECSPI_INT_TFEN (1 << 2)
+#define ARK_ECSPI_INT_RREN (1 << 3)
+#define ARK_ECSPI_INT_TCEN (1 << 7)
+
+#define ARK_ECSPI_DMA      0x14
+#define ARK_ECSPI_DMA_TX_WML(wml)	((wml) & 0x3f)
+#define ARK_ECSPI_DMA_RX_WML(wml)	((((wml) & 0x3f) - 1) << 16)
+#define ARK_ECSPI_DMA_RXT_WML(wml)	(((wml) & 0x3f) << 24)
+
+#define ARK_ECSPI_DMA_TEDEN		(1 << 7)
+#define ARK_ECSPI_DMA_RXDEN		(1 << 23)
+#define ARK_ECSPI_DMA_RXTDEN		(1UL << 31)
+
+#define ARK_ECSPI_STAT		0x18
+#define ARK_ECSPI_STAT_REN		(1 << 8)
+#define ARK_ECSPI_STAT_RR		(1 << 3)
+
+#define ARK_ECSPI_TESTREG	0x20
+#define ARK_ECSPI_TESTREG_LBC	BIT(31)
 struct ark_ecspi_data;
 
 struct ark_spi_devtype_data {
@@ -134,45 +179,6 @@ static int ark_spi_bytes_per_word(const int bits_per_word)
 	return DIV_ROUND_UP(bits_per_word, BITS_PER_BYTE);
 }
 
-#define ARK_ECSPI_CTRL		0x08
-#define ARK_ECSPI_CTRL_ENABLE		(1 <<  0)
-#define ARK_ECSPI_CTRL_XCH		(1 <<  2)
-#define ARK_ECSPI_CTRL_SMC		(1 << 3)
-#define ARK_ECSPI_CTRL_MODE_MASK	(0xf << 4)
-#define ARK_ECSPI_CTRL_DRCTL(drctl)	((drctl) << 16)
-#define ARK_ECSPI_CTRL_POSTDIV_OFFSET	8
-#define ARK_ECSPI_CTRL_PREDIV_OFFSET	12
-#define ARK_ECSPI_CTRL_CS(cs)		((cs) << 18)
-#define ARK_ECSPI_CTRL_BL_OFFSET	20
-#define ARK_ECSPI_CTRL_BL_MASK		(0xfff << 20)
-
-#define ARK_ECSPI_CONFIG	0x0c
-#define ARK_ECSPI_CONFIG_SCLKPHA(cs)	(1 << ((cs) +  0))
-#define ARK_ECSPI_CONFIG_SCLKPOL(cs)	(1 << ((cs) +  4))
-#define ARK_ECSPI_CONFIG_SBBCTRL(cs)	(1 << ((cs) +  8))
-#define ARK_ECSPI_CONFIG_SSBPOL(cs)	(1 << ((cs) + 12))
-#define ARK_ECSPI_CONFIG_SCLKCTL(cs)	(1 << ((cs) + 20))
-
-#define ARK_ECSPI_INT		0x10
-#define ARK_ECSPI_INT_TEEN		(1 <<  0)
-#define ARK_ECSPI_INT_RREN		(1 <<  3)
-
-#define ARK_ECSPI_DMA      0x14
-#define ARK_ECSPI_DMA_TX_WML(wml)	((wml) & 0x3f)
-#define ARK_ECSPI_DMA_RX_WML(wml)	((((wml) & 0x3f) - 1) << 16)
-#define ARK_ECSPI_DMA_RXT_WML(wml)	(((wml) & 0x3f) << 24)
-
-#define ARK_ECSPI_DMA_TEDEN		(1 << 7)
-#define ARK_ECSPI_DMA_RXDEN		(1 << 23)
-#define ARK_ECSPI_DMA_RXTDEN		(1UL << 31)
-
-#define ARK_ECSPI_STAT		0x18
-#define ARK_ECSPI_STAT_REN		(1 << 8)
-#define ARK_ECSPI_STAT_RR		(1 << 3)
-
-#define ARK_ECSPI_TESTREG	0x20
-#define ARK_ECSPI_TESTREG_LBC	BIT(31)
-
 static void ark_spi_buf_rx_swap_u32(struct ark_ecspi_data *aspi)
 {
 	unsigned int val = readl(aspi->base + ARK_ECSPI_RXDATA);
@@ -298,6 +304,15 @@ static void ark_ecspi_intctrl(struct ark_ecspi_data *aspi, int enable)
 	if (enable & ARK_INT_RR)
 		val |= ARK_ECSPI_INT_RREN;
 
+	if (enable & ARK_INT_TC)
+		val |= ARK_ECSPI_INT_TCEN;
+
+	if (enable & ARK_INT_TF)
+		val |= ARK_ECSPI_INT_TFEN;
+
+	if (enable & ARK_INT_TR)
+		val |= ARK_ECSPI_INT_TREN;
+
 	writel(val, aspi->base + ARK_ECSPI_INT);
 }
 
@@ -324,7 +339,9 @@ static int ark_ecspi_config(struct ark_ecspi_data *aspi)
 	 * the same time.
 	 * So set master mode for all channels as we do not support slave mode.
 	 */
+#ifndef SPI1_SLAVE_MODE
 	ctrl |= ARK_ECSPI_CTRL_MODE_MASK;
+#endif
 
 	/*
 	 * Enable SPI_RDY handling (falling edge/level triggered).
@@ -339,10 +356,18 @@ static int ark_ecspi_config(struct ark_ecspi_data *aspi)
 	/* set chip select to use */
 	ctrl |= ARK_ECSPI_CTRL_CS(chip_select);
 
-	if (aspi->usedma)
+	if (aspi->usedma) {
+#ifdef SPI1_SLAVE_MODE
+		if (aspi->dma_message.send_buf)
+			ctrl |= (aspi->dma_message.length * 8 - 1) << ARK_ECSPI_CTRL_BL_OFFSET;
+		else
+			ctrl |= (32 - 1) << ARK_ECSPI_CTRL_BL_OFFSET;
+#else
 		ctrl |= (32 - 1) << ARK_ECSPI_CTRL_BL_OFFSET;
-	else
+#endif
+	} else {
 		ctrl |= (aspi->bits_per_word - 1) << ARK_ECSPI_CTRL_BL_OFFSET;
+	}
 
 	cfg |= ARK_ECSPI_CONFIG_SBBCTRL(chip_select);
 
@@ -409,7 +434,10 @@ static int ark_ecspi_config(struct ark_ecspi_data *aspi)
 			ARK_ECSPI_DMA_RXT_WML(aspi->wml) |
 			ARK_ECSPI_DMA_TEDEN | ARK_ECSPI_DMA_RXDEN |
 			ARK_ECSPI_DMA_RXTDEN, aspi->base + ARK_ECSPI_DMA);
-	else writel(0, aspi->base + ARK_ECSPI_DMA);
+	else
+		writel(ARK_ECSPI_DMA_RX_WML(aspi->wml) |
+			ARK_ECSPI_DMA_TX_WML(aspi->wml),
+			aspi->base + ARK_ECSPI_DMA);
 
 	return 0;
 }
@@ -422,8 +450,15 @@ static int ark_ecspi_rx_available(struct ark_ecspi_data *aspi)
 static void ark_ecspi_reset(struct ark_ecspi_data *aspi)
 {
 	/* drain receive buffer */
-	while (ark_ecspi_rx_available(aspi))
-		readl(aspi->base + ARK_ECSPI_RXDATA);
+	/* while (ark_ecspi_rx_available(aspi))
+		readl(aspi->base + ARK_ECSPI_RXDATA); */
+	unsigned int ctrl = readl(aspi->base + ARK_ECSPI_CTRL);
+
+	ctrl &= ~ARK_ECSPI_CTRL_ENABLE;
+	writel(ctrl, aspi->base + ARK_ECSPI_CTRL);
+	udelay(10);
+	ctrl |= ARK_ECSPI_CTRL_ENABLE;
+	writel(ctrl, aspi->base + ARK_ECSPI_CTRL);
 }
 
 static struct ark_spi_devtype_data ark_ecspi_devtype_data = {
@@ -514,7 +549,7 @@ static int ark_spi_setupxfer(struct ark_ecspi_data *aspi,
 	else
 		aspi->word_mask = mask;
 
-	aspi->devtype_data->config(aspi);
+	// aspi->devtype_data->config(aspi);
 
 	return 0;
 }
@@ -549,7 +584,7 @@ static bool ark_spi_can_dma(struct ark_ecspi_data *aspi, struct spi_message *tra
 	remainder = transfer->length & 3;
 	len = transfer->length - remainder;
 
-	if (len < USE_DMA_THRESHOLD)
+	if ((len < USE_DMA_MIN_THRESHOLD) || (len > USE_DMA_MAX_THRESHOLD))
 		return false;
 
 	if ((u32)transfer->send_buf & 3 || (u32)transfer->recv_buf & 3)
@@ -604,8 +639,6 @@ static int ark_spi_sdma_init(struct ark_ecspi_data *aspi)
 {
 	int ret;
 
-	aspi->wml = aspi->devtype_data->fifo_size / 2;
-
 	/* Prepare for TX DMA: */
 	aspi->dma_tx = dma_request_channel(ECSPI_TX_DMA_CH);
 	if (IS_ERR(aspi->dma_tx)) {
@@ -742,12 +775,17 @@ static int ark_spi_pio_xfer(struct ark_ecspi_data *aspi, struct spi_message *mes
 		if (!tx_dummy_buf) return -ENOMEM;
 		aspi->tx_buf = tx_dummy_buf;
 		memcpy(tx_dummy_buf, message->send_buf, message->length);
-	} else aspi->tx_buf = message->send_buf;
+	} else {
+		aspi->tx_buf = message->send_buf;
+	}
+
 	if ((unsigned int)message->recv_buf & 3) {
 		rx_dummy_buf = pvPortMalloc(message->length);
 		if (!rx_dummy_buf) return -ENOMEM;
 		aspi->rx_buf = rx_dummy_buf;
-	} else aspi->rx_buf = message->recv_buf;
+	} else {
+		aspi->rx_buf = message->recv_buf;
+	}
 
 	aspi->remainder = aspi->count = message->length;
 	aspi->read_u32 = 1;
@@ -756,7 +794,7 @@ static int ark_spi_pio_xfer(struct ark_ecspi_data *aspi, struct spi_message *mes
 
 	ark_spi_push(aspi);
 
-	aspi->devtype_data->intctrl(aspi, ARK_INT_TE);
+	aspi->devtype_data->intctrl(aspi, ARK_INT_TR);
 
 	transfer_timeout = ark_spi_calculate_timeout(aspi, message->length);
 	if (xQueueReceive(aspi->xfer_done, NULL, transfer_timeout) != pdTRUE) {
@@ -768,11 +806,15 @@ static int ark_spi_pio_xfer(struct ark_ecspi_data *aspi, struct spi_message *mes
 	} else {
 		if (rx_dummy_buf)
 			memcpy(message->recv_buf, rx_dummy_buf, message->length);
+
 		ret = message->length;
 	}
 
-	if (rx_dummy_buf) vPortFree(rx_dummy_buf);
-	if (tx_dummy_buf) vPortFree(tx_dummy_buf);
+	if (rx_dummy_buf)
+		vPortFree(rx_dummy_buf);
+
+	if (tx_dummy_buf)
+		vPortFree(tx_dummy_buf);
 
 	return ret;
 }
@@ -789,8 +831,12 @@ static int ecspi_xfer(struct spi_slave *slave, struct spi_message *message)
 	struct ark_ecspi_data *aspi = (struct ark_ecspi_data *)slave;
 	int ret = 0;
 
+	ark_ecspi_reset(aspi);
+
+#ifndef SPI1_SLAVE_MODE
 	if (message->cs_take)
 		ark_spi_chipselect(aspi, 1);
+#endif
 
 	if (ark_spi_can_dma(aspi, message))
 		aspi->usedma = 1;
@@ -811,8 +857,10 @@ static int ecspi_xfer(struct spi_slave *slave, struct spi_message *message)
 
 	ret = ark_spi_pio_xfer(aspi, message);
 end:
+#ifndef SPI1_SLAVE_MODE
 	if (message->cs_release)
 		ark_spi_chipselect(aspi, 0);
+#endif
 
 	return ret;
 };
@@ -826,6 +874,7 @@ static int ark_ecspi_probe(struct ark_ecspi_data *aspi, char *spi_bus_name)
 	aspi->xfer_done = xQueueCreate(1, 0);
 	request_irq(aspi->irq, 0, ark_spi_isr, aspi);
 
+	aspi->wml = aspi->devtype_data->fifo_size / 2;
 	if (aspi->devtype_data->has_dmamode) {
 		ret = ark_spi_sdma_init(aspi);
 		if (ret < 0)
@@ -849,6 +898,8 @@ int ecspi_init(void)
 		return -ENOMEM;
 	memset(aspi1, 0, sizeof(struct ark_ecspi_data));
 
+	sys_soft_reset(softreset_ssp1);
+
 	aspi1->base = REGS_SPI1_BASE;
 	aspi1->irq = SPI1_IRQn;
 	aspi1->spi_clk = ulClkGetRate(CLK_SPI1);

amt630hv160-freertos-beta/ArkmicroFiles/libcpu-amt630hv160/source/wrap.c

@@ -3,201 +3,258 @@
 #include "FreeRTOS.h"
 #include "ff_stdio.h"
 
-
-#define WRAP_CTL_INRSTATUS              	 (*(volatile unsigned int *)(REGS_WRAP_BASE + 0x00))//00
-#define WRAP_CTL_WORK_EN         			 (*(volatile unsigned int *)(REGS_WRAP_BASE + 0x04))//01
-#define WRAP_CTL_02              			 (*(volatile unsigned int *)(REGS_WRAP_BASE + 0x08))//02
-#define WRAP_CTL_INTER_CLR       			 (*(volatile unsigned int *)(REGS_WRAP_BASE + 0x0C))//03
-#define WRAP_CTL_INTER_MASK      			 (*(volatile unsigned int *)(REGS_WRAP_BASE + 0x10))//04
-#define WRAP_CTL_05              			 (*(volatile unsigned int *)(REGS_WRAP_BASE + 0x14))//05
-#define WRAP_CTL_06              			 (*(volatile unsigned int *)(REGS_WRAP_BASE + 0x18))//06
-#define WRAP_CTL_07              			 (*(volatile unsigned int *)(REGS_WRAP_BASE + 0x1C))//07
-
-#define WRAP_CTL_08              			 (*(volatile unsigned int *)(REGS_WRAP_BASE + 0x20))//08
-
-#define WRAP_CTL_FISHEYE_H_W_INIT_S0         (*(volatile unsigned int *)(REGS_WRAP_BASE + 0x2C))//0b
-#define WRAP_CTL_FISHEYE_H_W_INIT_S1         (*(volatile unsigned int *)(REGS_WRAP_BASE + 0x30))
-#define WRAP_CTL_FISHEYE_H_W_INIT_S2         (*(volatile unsigned int *)(REGS_WRAP_BASE + 0x34))
-#define WRAP_CTL_FISHEYE_H_W_INIT_S3         (*(volatile unsigned int *)(REGS_WRAP_BASE + 0x38))
-#define WRAP_CTL_FISHEYE_H_W_INIT_S4         (*(volatile unsigned int *)(REGS_WRAP_BASE + 0x3C))
-#define WRAP_CTL_FISHEYE_H_W_INIT_S5         (*(volatile unsigned int *)(REGS_WRAP_BASE + 0x40))
-#define WRAP_CTL_RD_FADDR_Y_S0               (*(volatile unsigned int *)(REGS_WRAP_BASE + 0x44))//11
-#define WRAP_CTL_RD_FADDR_Y_S1               (*(volatile unsigned int *)(REGS_WRAP_BASE + 0x48))//12
-#define WRAP_CTL_RD_FADDR_Y_S2               (*(volatile unsigned int *)(REGS_WRAP_BASE + 0x4C))//13
-#define WRAP_CTL_RD_FADDR_Y_S3               (*(volatile unsigned int *)(REGS_WRAP_BASE + 0x50))//14
-#define WRAP_CTL_RD_FADDR_Y_S4               (*(volatile unsigned int *)(REGS_WRAP_BASE + 0x54))//15
-#define WRAP_CTL_RD_FADDR_Y_S5               (*(volatile unsigned int *)(REGS_WRAP_BASE + 0x58))//16
-#define WRAP_CTL_RD_HEIGHT_WIDETH_YUV_S0     (*(volatile unsigned int *)(REGS_WRAP_BASE + 0x5C))//17
-#define WRAP_CTL_RD_HEIGHT_WIDETH_YUV_S1     (*(volatile unsigned int *)(REGS_WRAP_BASE + 0x60))//18
-#define WRAP_CTL_RD_HEIGHT_WIDETH_YUV_S2     (*(volatile unsigned int *)(REGS_WRAP_BASE + 0x64))//19
-#define WRAP_CTL_RD_HEIGHT_WIDETH_YUV_S3     (*(volatile unsigned int *)(REGS_WRAP_BASE + 0x68))//1a
-#define WRAP_CTL_RD_HEIGHT_WIDETH_YUV_S4     (*(volatile unsigned int *)(REGS_WRAP_BASE + 0x6C))//1b
-#define WRAP_CTL_RD_HEIGHT_WIDETH_YUV_S5     (*(volatile unsigned int *)(REGS_WRAP_BASE + 0x70))//1c
-#define WRAP_CTL_RD_LINE_WIDE_INIT_S0        (*(volatile unsigned int *)(REGS_WRAP_BASE + 0x74))//1d
-#define WRAP_CTL_RD_LINE_WIDE_INIT_S1        (*(volatile unsigned int *)(REGS_WRAP_BASE + 0x78))//1e
-#define WRAP_CTL_RD_LINE_WIDE_INIT_S2        (*(volatile unsigned int *)(REGS_WRAP_BASE + 0x7c))//1f
-#define WRAP_CTL_RD_LINE_WIDE_INIT_S3        (*(volatile unsigned int *)(REGS_WRAP_BASE + 0x80))//20
-#define WRAP_CTL_RD_LINE_WIDE_INIT_S4        (*(volatile unsigned int *)(REGS_WRAP_BASE + 0x84))//21
-#define WRAP_CTL_RD_LINE_WIDE_INIT_S5        (*(volatile unsigned int *)(REGS_WRAP_BASE + 0x88))//22
-
-
-#define WRAP_CTL_RD_FADDR_ML_S0              (*(volatile unsigned int *)(REGS_WRAP_BASE + 0xA0))//28
-#define WRAP_CTL_RD_FADDR_ML_S1              (*(volatile unsigned int *)(REGS_WRAP_BASE + 0xA4))//29
-#define WRAP_CTL_RD_FADDR_ML_S2              (*(volatile unsigned int *)(REGS_WRAP_BASE + 0xA8))//2a
-#define WRAP_CTL_RD_FADDR_ML_S3              (*(volatile unsigned int *)(REGS_WRAP_BASE + 0xAC))//2b
-#define WRAP_CTL_RD_FADDR_ML_S4              (*(volatile unsigned int *)(REGS_WRAP_BASE + 0xB0))//2c
-#define WRAP_CTL_RD_FADDR_ML_S5              (*(volatile unsigned int *)(REGS_WRAP_BASE + 0xB4))//2d
-#define WRAP_CTL_ML_HEIGHT_WIDETH_S0         (*(volatile unsigned int *)(REGS_WRAP_BASE + 0xB8))//2e
-#define WRAP_CTL_ML_HEIGHT_WIDETH_S1         (*(volatile unsigned int *)(REGS_WRAP_BASE + 0xBC))//2f
-#define WRAP_CTL_ML_HEIGHT_WIDETH_S2         (*(volatile unsigned int *)(REGS_WRAP_BASE + 0xC0))//30
-#define WRAP_CTL_ML_HEIGHT_WIDETH_S3         (*(volatile unsigned int *)(REGS_WRAP_BASE + 0xC4))//31
-#define WRAP_CTL_ML_HEIGHT_WIDETH_S4         (*(volatile unsigned int *)(REGS_WRAP_BASE + 0xC8))//32
-#define WRAP_CTL_ML_HEIGHT_WIDETH_S5         (*(volatile unsigned int *)(REGS_WRAP_BASE + 0xCC))//33
+//wrap register
+#define WRAP_CTL_INRSTATUS_REG				0x00	//00
+#define WRAP_CTL_WORK_EN_REG				0x04	//01
+#define WRAP_CTL_READ_ID_REG				0x08	//02
+#define WRAP_CTL_INTER_CLR_REG				0x0C	//03
+#define WRAP_CTL_INTER_MASK_REG				0x10	//04
+#define WRAP_CTL_READ_WIDTH_S0_S1_REG0		0x14	//05
+#define WRAP_CTL_READ_WIDTH_S2_S3_REG1		0x18	//06
+#define WRAP_CTL_READ_WIDTH_S4_S5_REG2		0x1C	//07
+
+#define WRAP_CTL_FISHEYE_H_W_INIT_S0		0x2C	//0b
+#define WRAP_CTL_FISHEYE_H_W_INIT_S1		0x30	//0c
+#define WRAP_CTL_FISHEYE_H_W_INIT_S2		0x34	//0d
+#define WRAP_CTL_FISHEYE_H_W_INIT_S3		0x38	//0d
+#define WRAP_CTL_FISHEYE_H_W_INIT_S4		0x3C	//0e
+#define WRAP_CTL_FISHEYE_H_W_INIT_S5		0x40	//10
+#define WRAP_CTL_RD_FADDR_Y_S0				0x44	//11
+#define WRAP_CTL_RD_FADDR_Y_S1				0x48	//12
+#define WRAP_CTL_RD_FADDR_Y_S2				0x4C	//13
+#define WRAP_CTL_RD_FADDR_Y_S3				0x50	//14
+#define WRAP_CTL_RD_FADDR_Y_S4				0x54	//15
+#define WRAP_CTL_RD_FADDR_Y_S5				0x58	//16
+#define WRAP_CTL_RD_HEIGHT_WIDETH_YUV_S0	0x5C	//17
+#define WRAP_CTL_RD_HEIGHT_WIDETH_YUV_S1	0x60	//18
+#define WRAP_CTL_RD_HEIGHT_WIDETH_YUV_S2	0x64	//19
+#define WRAP_CTL_RD_HEIGHT_WIDETH_YUV_S3	0x68	//1a
+#define WRAP_CTL_RD_HEIGHT_WIDETH_YUV_S4	0x6C	//1b
+#define WRAP_CTL_RD_HEIGHT_WIDETH_YUV_S5	0x70	//1c
+#define WRAP_CTL_RD_LINE_WIDE_INIT_S0		0x74	//1d
+#define WRAP_CTL_RD_LINE_WIDE_INIT_S1		0x78	//1e
+#define WRAP_CTL_RD_LINE_WIDE_INIT_S2		0x7c	//1f
+#define WRAP_CTL_RD_LINE_WIDE_INIT_S3		0x80	//20
+#define WRAP_CTL_RD_LINE_WIDE_INIT_S4		0x84	//21
+#define WRAP_CTL_RD_LINE_WIDE_INIT_S5		0x88	//22
+
+#define WRAP_CTL_RD_FADDR_ML_S0				0xA0	//28
+#define WRAP_CTL_RD_FADDR_ML_S1				0xA4	//29
+#define WRAP_CTL_RD_FADDR_ML_S2				0xA8	//2a
+#define WRAP_CTL_RD_FADDR_ML_S3				0xAC	//2b
+#define WRAP_CTL_RD_FADDR_ML_S4				0xB0	//2c
+#define WRAP_CTL_RD_FADDR_ML_S5				0xB4	//2d
+#define WRAP_CTL_ML_HEIGHT_WIDETH_S0		0xB8	//2e
+#define WRAP_CTL_ML_HEIGHT_WIDETH_S1		0xBC	//2f
+#define WRAP_CTL_ML_HEIGHT_WIDETH_S2		0xC0	//30
+#define WRAP_CTL_ML_HEIGHT_WIDETH_S3		0xC4	//31
+#define WRAP_CTL_ML_HEIGHT_WIDETH_S4		0xC8	//32
+#define WRAP_CTL_ML_HEIGHT_WIDETH_S5		0xCC	//33
 
 //畸变校正图坐标读取,整个坐标图在memory的一行宽度
-#define WRAP_CTL_IMG_R_S1_S0              	 (*(volatile unsigned int *)(REGS_WRAP_BASE + 0xD0))//34
-#define WRAP_CTL_IMG_R_S3_S2             	 (*(volatile unsigned int *)(REGS_WRAP_BASE + 0xD4))//35
-#define WRAP_CTL_IMG_R_S5_S4              	 (*(volatile unsigned int *)(REGS_WRAP_BASE + 0xD8))//36
+#define WRAP_CTL_IMG_R_S1_S0				0xD0	//34
+#define WRAP_CTL_IMG_R_S3_S2				0xD4	//35
+#define WRAP_CTL_IMG_R_S5_S4				0xD8	//36
 
 //畸变校正图回写memory时，memory中一行的宽度
-#define WRAP_CTL_IMG_W_MRM_S1_S0             (*(volatile unsigned int *)(REGS_WRAP_BASE + 0xDC))//37
-#define WRAP_CTL_IMG_W_MRM_S3_S2             (*(volatile unsigned int *)(REGS_WRAP_BASE + 0xE0))//38
-#define WRAP_CTL_IMG_W_MRM_S5_S4             (*(volatile unsigned int *)(REGS_WRAP_BASE + 0xE4))//39
+#define WRAP_CTL_IMG_W_MRM_S1_S0			0xDC	//37
+#define WRAP_CTL_IMG_W_MRM_S3_S2			0xE0	//38
+#define WRAP_CTL_IMG_W_MRM_S5_S4			0xE4	//39
 
 //畸变校正图，分段数据的存储起始地址
-#define WRAP_CTL_WR_FADDR_RGB_S0             (*(volatile unsigned int *)(REGS_WRAP_BASE + 0xE8))//3a
-#define WRAP_CTL_WR_FADDR_RGB_S1             (*(volatile unsigned int *)(REGS_WRAP_BASE + 0xEC))//3b
-#define WRAP_CTL_WR_FADDR_RGB_S2             (*(volatile unsigned int *)(REGS_WRAP_BASE + 0xF0))//3c
-#define WRAP_CTL_WR_FADDR_RGB_S3             (*(volatile unsigned int *)(REGS_WRAP_BASE + 0xF4))//3d
-#define WRAP_CTL_WR_FADDR_RGB_S4             (*(volatile unsigned int *)(REGS_WRAP_BASE + 0xF8))//3e
-#define WRAP_CTL_WR_FADDR_RGB_S5             (*(volatile unsigned int *)(REGS_WRAP_BASE + 0xFC))//3f
-
-#define WRAP_MAX_WIDTH		1024//VIN_WIDTH
-#define WRAP_MAX_HEIGHT		600//VIN_HEIGHTs
-
-static void *srcwrap_buf = NULL;
-static void *srcwrap_buf2 = NULL;
-static void *deswrap_buf = NULL;
-static void *coordinatewrap_buf = NULL;
-static TaskHandle_t wrap_task;
-QueueHandle_t xDataQueue;
+#define WRAP_CTL_WR_FADDR_RGB_S0			0xE8	//3a
+#define WRAP_CTL_WR_FADDR_RGB_S1			0xEC	//3b
+#define WRAP_CTL_WR_FADDR_RGB_S2			0xF0	//3c
+#define WRAP_CTL_WR_FADDR_RGB_S3			0xF4	//3d
+#define WRAP_CTL_WR_FADDR_RGB_S4			0xF8	//3e
+#define WRAP_CTL_WR_FADDR_RGB_S5			0xFC	//3f
+
+#define WRAP_MAX_WIDTH						800		//VIN_WIDTH
+#define WRAP_MAX_HEIGHT						480		//VIN_HEIGHTs
+#define WRAP_SEC_MAX_WHDTH					1024
+
+//enum
+enum wrap_sections {
+	SECT_1 = 0x1,
+	SECT_2 = 0x3,
+};
+
+//structure
+struct wrap_obj {
+	enum wrap_sections sect;	//分段数配置 当分段数位1时，srcwide不得超过1024
+	unsigned int srcwide;
+	unsigned int srcheight;
+	unsigned int *srcwrap_buf;
+	unsigned int *coordinatewrap_buf;
+	unsigned int *deswrap_buf;
+};
+
+//global variable
+static TaskHandle_t wrap_task = NULL;
+
+//external
 extern int usb_wait_stor_dev_pluged(uint32_t timeout);
 
-static void Wrap_interupt_handler(void *param)
+static void wrap_interupt_handler(void *param)
 {
 	unsigned int val;
-	val = WRAP_CTL_INRSTATUS;
-	WRAP_CTL_INTER_CLR = 1;
-	if(val>>5 & 0x1)
-	{
-		printf("write back error!!\n");
+
+	val = readl(REGS_WRAP_BASE + WRAP_CTL_INRSTATUS_REG);
+	writel(1, REGS_WRAP_BASE + WRAP_CTL_INTER_CLR_REG);
+
+	if ((val >> 5) & 0x1) {
+		printf("%s write back error!!\n", __func__);
 	}
-	if(val>>3 & 0x1)
-	{
-		xTaskNotifyFromISR(wrap_task, 0, eSetValueWithOverwrite, 0);
-		printf("Fish eye work down!!\n");
+
+	if ((val >> 3) & 0x1) {
+		if (wrap_task)
+			xTaskNotifyFromISR(wrap_task, 0, eSetValueWithOverwrite, 0);
+		printf("%s Fish eye work down!!\n", __func__);
 	}
 }
 
-static void wrap_display(void *param)
+static void wrap_configure(struct wrap_obj *wo)
 {
-	unsigned int val;
-	unsigned int srcwide,srcheight;
+	unsigned int value = 0;
+	unsigned int fml_whc_sel;
+	unsigned int fml_bit_sel;
 	unsigned int Pic_src_init_sel;
 	unsigned int wb_bus_bvalid_dsen;
 	unsigned int wb_wait_en;
-	unsigned int fml_whc_sel;
-	unsigned int fml_bit_sel;
-	unsigned int width_mode;
-	unsigned int Sections;
+
+	//wrap_ram_sel
+	value = readl(REGS_SYSCTL_BASE + 0x1c8);
+	value |= (1 << 0);
+	writel(value, REGS_SYSCTL_BASE + 0x1c8);
+
+	Pic_src_init_sel = 0;	//set srcpicture mode select bit22
+	wb_bus_bvalid_dsen = 0;	//interrupt mode bit20
+	wb_wait_en = 0;			//set if wait bresp
+	fml_whc_sel = 1;
+	fml_bit_sel = 0;
+
+	//softreset
+	value = readl(REGS_WRAP_BASE + WRAP_CTL_INRSTATUS_REG);
+	value |= (1 << 1);
+	writel(value, REGS_WRAP_BASE + WRAP_CTL_INRSTATUS_REG);
+
+	value = readl(REGS_WRAP_BASE + WRAP_CTL_INRSTATUS_REG);
+	value &= ~((0x3F << 8) | (0x1 << 16) | (0x1 << 17) | (0x1 << 18) | (0x1 << 20) | (0x1 << 19) | (0x1 << 22));
+	value |= ((wo->sect << 8) |
+		(fml_bit_sel << 16) |
+		(fml_whc_sel << 17) |
+		(wb_wait_en << 19) |
+		(wb_bus_bvalid_dsen << 20) |
+		(Pic_src_init_sel << 22));
+	writel(value, REGS_WRAP_BASE + WRAP_CTL_INRSTATUS_REG);
+
+	writel((wo->srcheight << 16) | (wo->srcwide << 0), REGS_WRAP_BASE + WRAP_CTL_FISHEYE_H_W_INIT_S0);
+
+	//源图，分段，Y(rgb)通道的起始地址
+	writel((unsigned int)wo->srcwrap_buf, REGS_WRAP_BASE + WRAP_CTL_RD_FADDR_Y_S0);
+
+	//源图分段的高度和宽度
+	writel((wo->srcwide << 16) | (wo->srcwide << 0), REGS_WRAP_BASE + WRAP_CTL_RD_HEIGHT_WIDETH_YUV_S0);
+
+	//分段1源图的起始点在原图中的垂直位置和水平位置
+	writel((0 << 16) | (0 << 0), REGS_WRAP_BASE + WRAP_CTL_RD_LINE_WIDE_INIT_S0);
+
+	//畸变校正图坐标，分段，映射坐标的起始地址配置
+	writel((unsigned int)wo->coordinatewrap_buf, REGS_WRAP_BASE + WRAP_CTL_RD_FADDR_ML_S0);
+
+	//畸变校正图坐标，分段的高度和宽度
+	writel((wo->srcheight << 16) | (wo->srcwide << 0), REGS_WRAP_BASE + WRAP_CTL_ML_HEIGHT_WIDETH_S0);
+
+	//畸变校正图坐标读取,整个坐标图在memory的一行宽度
+	writel((wo->srcwide << 16) | (wo->srcwide << 0), REGS_WRAP_BASE + WRAP_CTL_IMG_R_S1_S0);
+
+	//畸变校正图回写memory时，memory中一行的宽度
+	writel((wo->srcwide << 16) | (wo->srcwide << 0), REGS_WRAP_BASE + WRAP_CTL_IMG_W_MRM_S1_S0);
+
+	//畸变校正图，分段，数据的存储起始地址
+	writel((unsigned int)wo->deswrap_buf, REGS_WRAP_BASE + WRAP_CTL_WR_FADDR_RGB_S0);
+
+	if (wo->sect == SECT_2) {
+		writel((wo->srcheight << 16) | (wo->srcwide << 0), REGS_WRAP_BASE + WRAP_CTL_FISHEYE_H_W_INIT_S1);
+		writel((unsigned int)wo->srcwrap_buf + (wo->srcwide / 2 - 4) * 4, REGS_WRAP_BASE + WRAP_CTL_RD_FADDR_Y_S1);
+		writel((wo->srcheight << 16) | ((wo->srcwide / 2) << 0), REGS_WRAP_BASE + WRAP_CTL_RD_HEIGHT_WIDETH_YUV_S0);
+		writel((wo->srcheight << 16) | ((wo->srcwide / 2) << 0), REGS_WRAP_BASE + WRAP_CTL_RD_HEIGHT_WIDETH_YUV_S1);
+		writel((0 << 16) | ((wo->srcwide / 2 - 4) << 0), REGS_WRAP_BASE + WRAP_CTL_RD_LINE_WIDE_INIT_S1);
+		writel((unsigned int)wo->coordinatewrap_buf + (wo->srcwide / 2) * 8, REGS_WRAP_BASE + WRAP_CTL_RD_FADDR_ML_S1);
+		writel((wo->srcheight << 16) | ((wo->srcwide / 2) << 0), REGS_WRAP_BASE + WRAP_CTL_ML_HEIGHT_WIDETH_S0);
+		writel((wo->srcheight << 16) | ((wo->srcwide / 2) << 0), REGS_WRAP_BASE + WRAP_CTL_ML_HEIGHT_WIDETH_S1);
+		writel((wo->srcwide << 16) | (wo->srcwide << 0), REGS_WRAP_BASE + WRAP_CTL_IMG_R_S3_S2);
+		writel((wo->srcwide << 16) | (wo->srcwide << 0), REGS_WRAP_BASE + WRAP_CTL_IMG_R_S5_S4);
+		writel((wo->srcwide << 16) | (wo->srcwide << 0), REGS_WRAP_BASE + WRAP_CTL_IMG_W_MRM_S3_S2);
+		writel((wo->srcwide << 16) | (wo->srcwide << 0), REGS_WRAP_BASE + WRAP_CTL_IMG_W_MRM_S5_S4);
+		writel((unsigned int)wo->deswrap_buf + (wo->srcwide / 2) * 4, REGS_WRAP_BASE + WRAP_CTL_WR_FADDR_RGB_S1);
+	}
+
+	request_irq(WRAP_IRQn, 0, wrap_interupt_handler, NULL);
+
+	writel(0, REGS_WRAP_BASE + WRAP_CTL_INTER_MASK_REG);
+	value = readl(REGS_WRAP_BASE + WRAP_CTL_READ_ID_REG);
+	value |= (0x55 << 12);
+	writel(value, REGS_WRAP_BASE + WRAP_CTL_READ_ID_REG);
+	writel(1, REGS_WRAP_BASE + WRAP_CTL_WORK_EN_REG);
+}
+
+static void wrap_display_demo(void *param)
+{
+	struct wrap_obj *wo = (struct wrap_obj *)param;
 	uint32_t ulNotifiedValue;
 	unsigned int status;
 	FF_FILE *fp;
 	size_t filesize;
 	int rlen;
 
-	srcwide = 800;
-	srcheight = 480;
-
-	Pic_src_init_sel = 0;//set srcpicture mode select bit22
-	wb_bus_bvalid_dsen = 0;//interrupt mode bit20
-	wb_wait_en  = 0;//bit19
-	fml_whc_sel = 1;//bit17
-	fml_bit_sel = 0;//bit16
-	Sections = 0x1; //bit8--13
-	width_mode = 0;//0 --1024;1---512
+	if (!wo) {
+		printf("%s Invalid wo.\n", __func__);
+		goto end;
+	}
 
 	status = usb_wait_stor_dev_pluged(portMAX_DELAY);
-	if (status == 0) {
-		fp = ff_fopen("/usb/Distort_480x800_a888.bin", "rb");
-		filesize = ff_filelength(fp);
-		rlen = ff_fread(srcwrap_buf, 1, filesize, fp);
-		if (rlen <= 0) {
-			printf("read data fail.\n");
-		}
-
-		if (fp)
-			ff_fclose(fp);
-
-		fp = ff_fopen("/usb/out.bin", "rb");
-		filesize = ff_filelength(fp);
-		rlen = ff_fread(coordinatewrap_buf, 1, filesize, fp);
-		if (rlen <= 0) {
-			printf("read data fail.\n");
-		}
-
-		if (fp)
-			ff_fclose(fp);
+	if (status != 0) {
+		printf("%s usb_wait_stor_dev_pluged fail\n", __func__);
+		goto end;
 	}
-	//wrap ram切换
-	unsigned int value = 0;
-	value =  (*(volatile unsigned int *)(0x50000000 + 0x1c8));
-	value |= (1<<0);
-	(*(volatile unsigned int *)(0x50000000 + 0x1c8)) = value;
-
-//softreset
-	WRAP_CTL_INRSTATUS |= 1<<1;
-
-	val = WRAP_CTL_INRSTATUS;
-	val &=~(0x3F<<8 | 0x1 << 16 | 0x1 << 17| 0x1 << 18 | 0x1 << 20| 0x1 << 19 | 0x1 << 22 );
-	val |= Sections<<8 | fml_bit_sel<<16 | fml_whc_sel<<17 | width_mode<<18 | wb_wait_en<<19 | wb_bus_bvalid_dsen<<20 | Pic_src_init_sel<<22;
-	WRAP_CTL_INRSTATUS = val;
-
 
-//原图的高度和高度
-	WRAP_CTL_FISHEYE_H_W_INIT_S0 = (480<<16)|(800<<0);
-
-//源图，分段，Y(rgb)通道的起始地址
-	WRAP_CTL_RD_FADDR_Y_S0 = (unsigned int )srcwrap_buf;
-
-//源图分段的高度和宽度
-	WRAP_CTL_RD_HEIGHT_WIDETH_YUV_S0 = (480<<16)|(800<<0);
-
-//分段1源图的起始点在原图中的垂直位置和水平位置
-	WRAP_CTL_RD_LINE_WIDE_INIT_S0 = (0<<16)|(0<<0);
-
-//畸变校正图坐标，分段，映射坐标的起始地址配置
-	WRAP_CTL_RD_FADDR_ML_S0 = (unsigned int)coordinatewrap_buf;
+	fp = ff_fopen("/usb/Distort_480x800_a888.bin", "rb");
+	if (!fp) {
+		printf("%s open file fail.\n", __func__);
+		goto end;
+	}
 
-//畸变校正图坐标，分段的高度和宽度
-	WRAP_CTL_ML_HEIGHT_WIDETH_S0 = (480<<16)|(800<<0);
+	filesize = ff_filelength(fp);
+	rlen = ff_fread(wo->srcwrap_buf, 1, filesize, fp);
+	if (rlen <= 0) {
+		printf("%s read data fail.\n", __func__);
+		ff_fclose(fp);
+		goto end;
+	}
 
-//畸变校正图坐标读取,整个坐标图在memory的一行宽度
-	WRAP_CTL_IMG_R_S1_S0 = (800<<16)|(800<<0);
+	if (fp)
+		ff_fclose(fp);
 
-//畸变校正图回写memory时，memory中一行的宽度
-	WRAP_CTL_IMG_W_MRM_S1_S0 = (800<<16)|(800<<0);
+	fp = ff_fopen("/usb/outij480_800.bin", "rb");
+	if (!fp) {
+		printf("%s open file fail.\n", __func__);
+		goto end;
+	}
 
-//畸变校正图，分段，数据的存储起始地址
-	WRAP_CTL_WR_FADDR_RGB_S0 = (unsigned int )deswrap_buf;
+	filesize = ff_filelength(fp);
+	rlen = ff_fread(wo->coordinatewrap_buf, 1, filesize, fp);
+	if (rlen <= 0) {
+		printf("%s read data fail.\n", __func__);
+		ff_fclose(fp);
+		goto end;
+	}
 
-	request_irq(WRAP_IRQn, 0, Wrap_interupt_handler, NULL);
-	WRAP_CTL_INTER_MASK = 0;
-	WRAP_CTL_02 |= 0x55<<12;
-	WRAP_CTL_WORK_EN = 1;
+	if (fp)
+		ff_fclose(fp);
 
-	//while(!wrap_work_down);
-	xTaskNotifyWait( 0x00, /* Don't clear any notification bits on entry. */
+	wrap_configure(wo);
+	xTaskNotifyWait(0x00, /* Don't clear any notification bits on entry. */
 			0xffffffff, /* Reset the notification value to 0 on exit. */
 			&ulNotifiedValue, /* Notified value pass out in ulNotifiedValue. */
 			portMAX_DELAY);
@@ -208,54 +265,82 @@ static void wrap_display(void *param)
 	ark_lcd_set_osd_sync(LCD_UI_LAYER);
 	ark_lcd_osd_coeff_enable(LCD_VIDEO_LAYER, 1);
 	ark_lcd_osd_set_coeff(LCD_VIDEO_LAYER, 0xFF);
-	ark_lcd_set_osd_possition(LCD_VIDEO_LAYER, 560,120);
-	ark_lcd_set_osd_size(LCD_VIDEO_LAYER, srcwide, srcheight);
+	ark_lcd_set_osd_possition(LCD_VIDEO_LAYER, 0, 0);
+	ark_lcd_set_osd_size(LCD_VIDEO_LAYER, wo->srcwide, wo->srcheight);
 	ark_lcd_set_osd_format(LCD_VIDEO_LAYER, LCD_OSD_FORAMT_ARGB888);
-	ark_lcd_set_osd_yaddr(LCD_VIDEO_LAYER, (unsigned int)deswrap_buf);
+	ark_lcd_set_osd_yaddr(LCD_VIDEO_LAYER, (unsigned int)wo->deswrap_buf);
 	ark_lcd_osd_enable(LCD_VIDEO_LAYER, 1);
 	ark_lcd_set_osd_sync(LCD_VIDEO_LAYER);
 	ark_lcd_wait_for_vsync();
 
+end:
 	while(1)
 		vTaskDelay(portMAX_DELAY);
 }
 
 void wrap_demo(void)
 {
-	srcwrap_buf = (void *)pvPortMalloc(WRAP_MAX_WIDTH * WRAP_MAX_HEIGHT * 4);
-	if (!srcwrap_buf) {
-		printf("Src wrap buf malloc memory fail.\n");
-		return;
-	}
+	struct wrap_obj *wo;
 
-	deswrap_buf = (void *)pvPortMalloc(WRAP_MAX_WIDTH * WRAP_MAX_HEIGHT * 4);
-	if (!deswrap_buf) {
-		printf("Des wrap buf malloc memory fail.\n");
+	wo = pvPortMalloc(sizeof(struct wrap_obj));
+	if (!wo) {
+		printf("%s malloc wrap_obj fail!\n", __func__);
 		return;
 	}
+	memset(wo, 0, sizeof(struct wrap_obj));
 
-	coordinatewrap_buf = (void *)pvPortMalloc(WRAP_MAX_WIDTH * WRAP_MAX_HEIGHT * 5);
-	if (!coordinatewrap_buf) {
-		printf("Des wrap buf malloc memory fail.\n");
-		return;
-	}
-
-	memset(srcwrap_buf, 0, WRAP_MAX_WIDTH * WRAP_MAX_HEIGHT*4);
-	memset(deswrap_buf, 0, WRAP_MAX_WIDTH * WRAP_MAX_HEIGHT*4);
-	memset(coordinatewrap_buf, 0, WRAP_MAX_WIDTH * WRAP_MAX_HEIGHT * 5);
+	wo->sect = SECT_1;
+	wo->srcwide = WRAP_MAX_WIDTH;
+	wo->srcheight = WRAP_MAX_HEIGHT;
 
-	printf(">>>srcwrap_buf 0x%x,deswrap_buf 0x%x,coordinatewrap_buf 0x%x\n",srcwrap_buf,deswrap_buf,coordinatewrap_buf);
-	if (xTaskCreate(wrap_display, "wrapdis", configMINIMAL_STACK_SIZE * 10, NULL,
-		configMAX_PRIORITIES - 3, &wrap_task) != pdPASS) {
-		printf("create itu display task fail.\n");
+	//源宽度小于1024的时候用分段1，源宽度大于1024用分段2
+	if (!((wo->sect == SECT_1 && wo->srcwide <= WRAP_SEC_MAX_WHDTH) || 
+		(wo->sect == SECT_2 && (WRAP_SEC_MAX_WHDTH < wo->srcwide) && (wo->srcwide <= LCD_WIDTH)))) {
+		printf("%s wrap set fail.\n", __func__);
+		goto err;
 	}
-}
 
+	wo->srcwrap_buf = (void *)pvPortMalloc(WRAP_MAX_WIDTH * WRAP_MAX_HEIGHT * 4);
+	if (!wo->srcwrap_buf) {
+		printf("%s Src wrap buf malloc memory fail.\n", __func__);
+		goto err;
+	}
 
+	wo->deswrap_buf = (void *)pvPortMalloc(WRAP_MAX_WIDTH * WRAP_MAX_HEIGHT * 4);
+	if (!wo->deswrap_buf) {
+		printf("%s Des wrap buf malloc memory fail.\n", __func__);
+		goto err;
+	}
 
+	wo->coordinatewrap_buf = (void *)pvPortMalloc(WRAP_MAX_WIDTH * WRAP_MAX_HEIGHT * 8);
+	if (!wo->coordinatewrap_buf) {
+		printf("%s Des wrap buf malloc memory fail.\n", __func__);
+		goto err;
+	}
 
+	memset(wo->srcwrap_buf, 0, WRAP_MAX_WIDTH * WRAP_MAX_HEIGHT * 4);
+	memset(wo->deswrap_buf, 0, WRAP_MAX_WIDTH * WRAP_MAX_HEIGHT * 4);
+	memset(wo->coordinatewrap_buf, 0, WRAP_MAX_WIDTH * WRAP_MAX_HEIGHT * 8);
 
+	printf(">>>srcwrap_buf 0x%x, deswrap_buf 0x%x, coordinatewrap_buf 0x%x\n",
+			wo->srcwrap_buf, wo->deswrap_buf, wo->coordinatewrap_buf);
+	if (xTaskCreate(wrap_display_demo, "wrapdis", configMINIMAL_STACK_SIZE * 10, (void *)wo,
+		configMAX_PRIORITIES - 3, &wrap_task) != pdPASS) {
+		printf("%s create wrap display task fail.\n", __func__);
+		goto err;
+	}
 
+	return;
+err:
+	if (wo->coordinatewrap_buf)
+		vPortFree(wo->coordinatewrap_buf);
 
+	if (wo->deswrap_buf)
+		vPortFree(wo->deswrap_buf);
 
+	if (wo->srcwrap_buf)
+		vPortFree(wo->srcwrap_buf);
 
+	if (wo)
+		vPortFree(wo);
+}