更新CPU_PLL锁相环时钟，从800MHZ修改为810MHZ，解决EMC认证(某频点)不通过的问题，同时同步调整CPU PLL下的SPI时钟频率。

amt630hv160-freertos-beta/lib/sfud/port/sfud_port.c

@@ -38,8 +38,8 @@
 #include "errno.h"
 #include "os_adapt.h"
 
-#define SFUD_SPI_MAX_HZ		80000000			//CPU (<=80MHz)	MCU (<=50MHz)
-#define SFUD_QSPI_MAX_HZ	50000000			//CPU (<=50MHz)	MCU (<=50MHz)
+#define SFUD_SPI_MAX_HZ		81000000			//CPU (<=81MHz)	MCU (<=50.625MHz)
+#define SFUD_QSPI_MAX_HZ	50625000			//CPU (<=50.625MHz)	MCU (<=50.625MHz)
 
 
 typedef struct {
@@ -53,8 +53,8 @@ static const sfud_spi_cfg_t spi_cfg_tab[] = {
 		.cfg = {
 			.mode = SPI_MODE_0,
 			.data_width = 8,
-			.max_hz = SFUD_SPI_MAX_HZ,			//<=80MHz
-			.qspi_max_hz = SFUD_QSPI_MAX_HZ,	//<=50MHz
+			.max_hz = SFUD_SPI_MAX_HZ,			//<=81MHz
+			.qspi_max_hz = SFUD_QSPI_MAX_HZ,	//<=50.625MHz
 		},
 	},
 
@@ -63,8 +63,8 @@ static const sfud_spi_cfg_t spi_cfg_tab[] = {
 		.cfg = {
 			.mode = SPI_MODE_0,
 			.data_width = 8,
-			.max_hz = SFUD_SPI_MAX_HZ,				//<=80MHz
-			.qspi_max_hz = SFUD_QSPI_MAX_HZ,		//<=50MHz
+			.max_hz = SFUD_SPI_MAX_HZ,			//<=81MHz
+			.qspi_max_hz = SFUD_QSPI_MAX_HZ,	//<=50.625MHz
 		},
 	},
 

amt630hv160-mcu/amt630hv160-mcu-iram/src/ArkmicroFiles/libcpu-amt630hv160/source/amt630hv160_clk.c

@@ -13,7 +13,7 @@
 #include "amt630hv160_lib.h"
 
 /* PLL config ----------------------------------------------------------------*/
-#define CPUPLL_FREQ				800000000	//800M
+#define CPUPLL_FREQ				810000000	//810M
 #define SYSPLL_FREQ				360000000	//360M
 #define DDRPLL_FREQ				360000000	//360M
 #define VPUPLL_FREQ				480000000	//480M
@@ -200,7 +200,11 @@ void CLK_SetFreq(u32 pllcfgreg, u64 freq, u8 ensprd)
 			refdiv = 4;
 			postdiv1 = 4;
 		}
-	} else {
+    } else if (pllcfgreg == (u32)&SYSCTRL->CPUPLL_CFG) {
+            postdiv2 = 1;
+			postdiv1 = 3;
+			refdiv = 4;
+    } else {
 		if (ensprd) {
 			printf("The pll does not support sprd.\n");
 			ensprd = 0;

amt630hv160-mcu/amt630hv160-mcu-iram/src/lib/sfud/port/sfud_port.c

@@ -35,8 +35,8 @@
 #include "snfud_def.h"
 #include "amt630hv160_lib.h"
 
-#define SFUD_SPI_MAX_HZ		50000000			//CPU (<=80MHz)	MCU (<=50MHz)
-#define SFUD_QSPI_MAX_HZ	50000000			//CPU (<=50MHz)	MCU (<=50MHz)
+#define SFUD_SPI_MAX_HZ		50625000			//CPU (<=80MHz)	MCU (<=50.625MHz)
+#define SFUD_QSPI_MAX_HZ	50625000			//CPU (<=50.625MHz)	MCU (<=50.625MHz)
 
 /* read the JEDEC SFDP command must run at <= 50 MHz, only for mcu */
 
@@ -51,8 +51,8 @@ static const sfud_spi_cfg_t spi_cfg_tab[] = {
 		.cfg = {
 			.mode = SPI_MODE_0,
 			.data_width = 8,
-			.max_hz = SFUD_SPI_MAX_HZ,			//<=50MHz
-			.qspi_max_hz = SFUD_QSPI_MAX_HZ,	//<=50MHz
+			.max_hz = SFUD_SPI_MAX_HZ,			//<=50.625MHz
+			.qspi_max_hz = SFUD_QSPI_MAX_HZ,	//<=50.625MHz
 		},
 	},
 
@@ -70,8 +70,8 @@ static const sfud_spi_cfg_t spi_cfg_tab[] = {
 		.cfg = {
 			.mode = SPI_MODE_0,
 			.data_width = 8,
-			.max_hz = SFUD_SPI_MAX_HZ,			//<=50MHz
-			.qspi_max_hz = SFUD_QSPI_MAX_HZ,	//<=50MHz
+			.max_hz = SFUD_SPI_MAX_HZ,			//<=50.625MHz
+			.qspi_max_hz = SFUD_QSPI_MAX_HZ,	//<=50.625MHz
 		},
 	},
 };

amt630hv160-mcu/amt630hv160-mcu-sram-nos/src/ArkmicroFiles/libcpu-amt630hv160/source/amt630hv160_clk.c

@@ -13,7 +13,7 @@
 #include "amt630hv160_lib.h"
 
 /* PLL config ----------------------------------------------------------------*/
-#define CPUPLL_FREQ				800000000	//800M
+#define CPUPLL_FREQ				810000000	//810M
 #define SYSPLL_FREQ				360000000	//360M
 #define DDRPLL_FREQ				360000000	//360M
 #define VPUPLL_FREQ				480000000	//480M
@@ -200,7 +200,11 @@ void CLK_SetFreq(u32 pllcfgreg, u64 freq, u8 ensprd)
 			refdiv = 4;
 			postdiv1 = 4;
 		}
-	} else {
+    } else if (pllcfgreg == (u32)&SYSCTRL->CPUPLL_CFG) {
+            postdiv2 = 1;
+			postdiv1 = 3;
+			refdiv = 4;
+    } else {
 		if (ensprd) {
 			printf("The pll does not support sprd.\n");
 			ensprd = 0;

amt630hv160-mcu/amt630hv160-mcu-sram-nos/src/lib/sfud/port/sfud_port.c

@@ -35,8 +35,8 @@
 #include "snfud_def.h"
 #include "amt630hv160_lib.h"
 
-#define SFUD_SPI_MAX_HZ		50000000			//CPU (<=80MHz)	MCU (<=50MHz)
-#define SFUD_QSPI_MAX_HZ	50000000			//CPU (<=50MHz)	MCU (<=50MHz)
+#define SFUD_SPI_MAX_HZ		50625000			//CPU (<=80MHz)	MCU (<=50.625MHz)
+#define SFUD_QSPI_MAX_HZ	50625000			//CPU (<=50.625MHz)	MCU (<=50.625MHz)
 
 /* read the JEDEC SFDP command must run at <= 50 MHz, only for mcu */
 
@@ -51,8 +51,8 @@ static const sfud_spi_cfg_t spi_cfg_tab[] = {
 		.cfg = {
 			.mode = SPI_MODE_0,
 			.data_width = 8,
-			.max_hz = SFUD_SPI_MAX_HZ,			//<=50MHz
-			.qspi_max_hz = SFUD_QSPI_MAX_HZ,	//<=50MHz
+			.max_hz = SFUD_SPI_MAX_HZ,			//<=50.625MHz
+			.qspi_max_hz = SFUD_QSPI_MAX_HZ,	//<=50.625MHz
 		},
 	},
 
@@ -70,8 +70,8 @@ static const sfud_spi_cfg_t spi_cfg_tab[] = {
 		.cfg = {
 			.mode = SPI_MODE_0,
 			.data_width = 8,
-			.max_hz = SFUD_SPI_MAX_HZ,			//<=50MHz
-			.qspi_max_hz = SFUD_QSPI_MAX_HZ,	//<=50MHz
+			.max_hz = SFUD_SPI_MAX_HZ,			//<=50.625MHz
+			.qspi_max_hz = SFUD_QSPI_MAX_HZ,	//<=50.625MHz
 		},
 	},
 };