#include "FreeRTOS.h"
#include "board.h"
#include "chip.h"

#define PINCTL_REG_BASE		REGS_SYSCTL_BASE

#define MAX_PINS_PER_GROUP	32
#define MAX_PIN_MUX_GROUP	4

typedef struct {
	short muxio;
	short pinval;
	int drive;
} xPin_t;

typedef struct _pin_mux{
	uint32_t mux_reg;
	uint32_t mux_offset;
	uint32_t mux_mask;
	uint32_t mux_val;
}pin_mux_t;

typedef struct {
	int	groupid;
	short pin_mux_num;
	pin_mux_t pin_mux[MAX_PIN_MUX_GROUP];
	short pins_num;
	xPin_t pins[MAX_PINS_PER_GROUP];
} xPinGroup_t;

/* typedef struct {

} xPinFunction_t; */

typedef struct {
	int reg;
	int offset;
	int mask;
} xPinmap_t;

static const xPinmap_t amt630hv160_pin_map[] = {
	{0xc0, 0, 0x3}, // gpio0
	{0xc0, 2, 0x3},
	{0xc0, 4, 0x3},
	{0xc0, 6, 0x3},
	{0xc0, 8, 0x3},
	{0xc0, 10, 0x3},
	{0xc0, 12, 0x3},
	{0xc0, 14, 0x3},
	{0xc0, 16, 0x3},
	{0xc0, 18, 0x3},
	{0xc0, 20, 0x3},
	{0xc0, 22, 0x3},
	{0xc0, 24, 0x3},
	{0xc0, 26, 0x3},
	{0xc0, 28, 0x3},
	{0xc0, 30, 0x3}, // gpio15

	{0xc4, 0, 0x3},	// gpio16
	{0xc4, 2, 0x3},
	{0xc4, 4, 0x3},
	{0xc4, 6, 0x3},
	{0xc4, 8, 0x3},
	{0xc4, 10, 0x3},
	{0xc4, 12, 0x3},
	{0xc4, 14, 0x3},
	{0xc4, 16, 0x3},
	{0xc4, 18, 0x3},
	{0xc4, 20, 0x3},
	{0xc4, 22, 0x3},
	{0xc4, 24, 0x3},
	{0xc4, 26, 0x3},
	{0xc4, 28, 0x3},
	{0xc4, 30, 0x3}, // gpio31

	{0xc8, 0, 0x3}, // gpio32
	{0xc8, 2, 0x3},
	{0xc8, 4, 0x3},
	{0xc8, 6, 0x3},
	{0xc8, 8, 0x3},
	{0xc8, 10, 0x3},
	{0xc8, 12, 0x3},
	{0xc8, 14, 0x3},
	{0xe4, 0, 0x3},
	{0xe4, 2, 0x3},
	{0xe4, 4, 0x3},
	{0xe4, 6, 0x3},
	{0xe4, 8, 0x3},
	{0xe4, 10, 0x3},
	{0xe4, 12, 0x3},
	{0xe4, 14, 0x3}, // gpio47

	{0xe4, 20, 0x3}, // gpio48
	{0xe4, 22, 0x3},
	{0xe4, 24, 0x3},
	{0xe4, 26, 0x3},
	{0xe4, 28, 0x3},
	{0xe4, 30, 0x3},
	{0xe8, 16, 0x3},
	{0xe8, 18, 0x3},
	{0xe8, 20, 0x3},
	{0xe8, 22, 0x3},
	{0xc8, 16, 0x3},
	{0xc8, 18, 0x3},
	{0xc8, 20, 0x3},
	{0xc8, 22, 0x3},
	{0xc8, 24, 0x3},
	{0xc8, 26, 0x3}, // gpio63

	{0xc8, 28, 0x3}, // gpio64
	{0xc8, 30, 0x3},
	{0xcc, 0, 0x3},
	{0xcc, 24, 0x3},
	{0xcc, 26, 0x3},
	{0xcc, 28, 0x3},
	{0xcc, 30, 0x3},
	{0xd0, 0, 0x3},
	{0xd0, 2, 0x3},
	{0xd0, 4, 0x3},
	{0xd0, 6, 0x3},
	{0xd0, 18, 0x3},
	{0xd0, 20, 0x3},
	{0xd0, 22, 0x3},
	{0xd0, 24, 0x3},
	{0xd0, 26, 0x3}, // gpio79


	{0xd4, 8, 0x3}, // gpio80
	{0xd4, 10, 0x3},
	{0xd4, 12, 0x3},
	{0xd4, 14, 0x3},
	{0xd4, 16, 0x3},
	{0xd4, 18, 0x3},
	{0xd4, 20, 0x3},
	{0xd4, 22, 0x3},
	{0xd4, 24, 0x3},
	{0xd4, 26, 0x3},
	{0xd8, 20, 0x3},
	{0xd8, 22, 0x3},
	{0xd8, 24, 0x3},
	{0xd8, 26, 0x3},
	{0xd8, 28, 0x3},
	{0xd8, 30, 0x3}, // gpio95

	{0xdc, 10, 0x3}, // gpio96
	{0xdc, 12, 0x3},
	{0xdc, 14, 0x3},
	{0xdc, 16, 0x3},
	{0xdc, 18, 0x3},
	{0xdc, 20, 0x3},
	{0xdc, 22, 0x3},
	{0xdc, 24, 0x3},
	{0xdc, 26, 0x3},
	{0xdc, 28, 0x3},
	{0xdc, 30, 0x3},
	{0xe0, 0, 0x3},
	{0xe0, 2, 0x3},
	{0xe0, 4, 0x3},
	{0xe0, 6, 0x3},
	{0xec, 0, 0x3}, // gpio111

	{0xec, 2, 0x3}, // gpio112
	{0xec, 4, 0x3},
	{0xec, 6, 0x3},
	{0xec, 8, 0x3},
	{0xec, 10, 0x3},
	{0xec, 12, 0x3},
	{0xec, 14, 0x3},
	{0xec, 16, 0x3},
	{0xec, 18, 0x3},
	{0xec, 20, 0x3},
	{0xec, 22, 0x3},
	{0xec, 24, 0x3},
	{0xec, 26, 0x3},
	{0xec, 28, 0x3},
	{0xec, 30, 0x3},
	{0xd0, 28, 0x3},// gpio127

	{0xF8, 0, 0x3},// gpio128
	{0xF8, 2, 0x3},
	{0xF8, 4, 0x3},
	{0xF8, 6, 0x3},
	{0xF8, 8, 0x3},
	{0xF8, 10, 0x3},
	{0xF8, 12, 0x3},
	{0xF8, 14, 0x3},
	{0xF8, 16, 0x3},
	{0xF8, 18, 0x3},
	{0xF8, 20, 0x3},
	{0xF8, 22, 0x3},
	{0xF8, 24, 0x3},
	{0xF8, 26, 0x3},
	{0xF8, 28, 0x3},
	{0xF8, 30, 0x3}, // gpio143

};
#define PIN_NUM		ARRAY_SIZE(amt630hv160_pin_map)


static const xPinmap_t amt630hv160_mcu_pin_map[] = {
	{0xc0, 0, 0x3}, // gpio0
	{0xc0, 2, 0x3},
	{0xc0, 4, 0x3},
	{0xc0, 6, 0x3},
	{0xc0, 8, 0x3},
	{0xc0, 10, 0x3},
	{0xc0, 12, 0x3},
	{0xc0, 14, 0x3},
	{0xc0, 16, 0x3},
	{0xc0, 18, 0x3},
	{0xc0, 20, 0x3},
	{0xc0, 22, 0x3},
	{0xc0, 24, 0x3},
	{0xc0, 26, 0x3},
	{0xc0, 28, 0x3},
	{0xc0, 30, 0x3}, // gpio15

	{0xc4, 0, 0x3},	// gpio16
	{0xc4, 2, 0x3},
	{0xc4, 4, 0x3},
	{0xc4, 6, 0x3},
	{0xc4, 8, 0x3},
	{0xc4, 10, 0x3},
	{0xc4, 12, 0x3},
	{0xc4, 14, 0x3},
	{0xc4, 16, 0x3},
	{0xc4, 18, 0x3},
	{0xc4, 20, 0x3},
	{0xc4, 22, 0x3},
	{0xc4, 24, 0x3},
	{0xc4, 26, 0x3},
	{0xc4, 28, 0x3},
	{0xc4, 30, 0x3}, // gpio31

	{0xc8, 0, 0x3}, // gpio32
	{0xc8, 2, 0x3},
	{0xc8, 4, 0x3},
	{0xc8, 6, 0x3},
	{0xc8, 8, 0x3},
	{0xc8, 10, 0x3},
	{0xc8, 12, 0x3},
	{0xc8, 14, 0x3},
	{0xe4, 0, 0x3},
	{0xe4, 2, 0x3},
	{0xe4, 4, 0x3},
	{0xe4, 6, 0x3},
	{0xe4, 8, 0x3},
	{0xe4, 10, 0x3},
	{0xe4, 12, 0x3},
	{0xe4, 14, 0x3}, // gpio47

	{0xe4, 20, 0x3}, // gpio48
	{0xe4, 22, 0x3},
	{0xe4, 24, 0x3},
	{0xe4, 26, 0x3},
	{0xe4, 28, 0x3},
	{0xe4, 30, 0x3},
	{0xe8, 16, 0x3},
	{0xe8, 18, 0x3},
	{0xe8, 20, 0x3},
	{0xe8, 22, 0x3},
	{0xc8, 16, 0x3},
	{0xc8, 18, 0x3},
	{0xc8, 20, 0x3},
	{0xc8, 22, 0x3},
	{0xc8, 24, 0x3},
	{0xc8, 26, 0x3}, // gpio63

	{0xc8, 28, 0x3}, // gpio64
	{0xc8, 30, 0x3},
	{0xcc, 0, 0x3},
	{0xcc, 2, 0x3},
	{0xcc, 4, 0x3},
	{0xcc, 6, 0x3},
	{0xcc, 8, 0x3},
	{0xcc, 10, 0x3},
	{0xcc, 12, 0x3},
	{0xcc, 14, 0x3},
	{0xcc, 16, 0x3},
	{0xcc, 18, 0x3},
	{0xcc, 20, 0x3},
	{0xcc, 22, 0x3},
	{0xd0, 8, 0x3},
	{0xd0, 10, 0x3}, // gpio79

	{0xd0, 12, 0x3}, // gpio80
	{0xd0, 14, 0x3},
	{0xd0, 16, 0x3},
	{0xd0, 28, 0x3},
	{0xd0, 30, 0x3},
	{0xd4, 0, 0x3},
	{0xd4, 2, 0x3},
	{0xd4, 4, 0x3},
	{0xd4, 6, 0x3},
	{0xd4, 28, 0x3},
	{0xd4, 30, 0x3},
	{0xd8, 0, 0x3},
	{0xd8, 2, 0x3},
	{0xd8, 4, 0x3},
	{0xd8, 6, 0x3},
	{0xd8, 8, 0x3},// gpio95


	{0xd8, 10, 0x3}, // gpio96
	{0xd8, 12, 0x3},
	{0xd8, 14, 0x3},
	{0xd8, 16, 0x3},
	{0xd8, 18, 0x3},
	{0xe4, 16, 0x3},
	{0xe4, 18, 0x3},
	{0xe8, 0, 0x3},
	{0xe8, 2, 0x3},
	{0xe8, 4, 0x3},
	{0xe8, 6, 0x3},
	{0xe8, 8, 0x3},
	{0xe8, 10, 0x3},
	{0xe8, 12, 0x3},
	{0xe8, 14, 0x3},
	{0xf0, 0, 0x3}, // gpio111

	{0xf0, 2, 0x3}, // gpio112
	{0xf0, 4, 0x3},
	{0xf0, 6, 0x3},
	{0xf0, 8, 0x3},
	{0xf0, 10, 0x3},
	{0xf0, 12, 0x3},
	{0xf0, 14, 0x3},
	{0xdc, 0, 0x3},
	{0xdc, 2, 0x3},
	{0xdc, 4, 0x3},
	{0xdc, 6, 0x3},
	{0xdc, 8, 0x3},
	{0Xd4, 8, 0x3},
	{0Xd4, 20, 0x3},// gpio125
	{0, 0, 0},	// reserved
	{0, 0, 0},	// reserved

	{0xF8, 0, 0x3},// gpio128
	{0xF8, 2, 0x3},
	{0xF8, 4, 0x3},
	{0xF8, 6, 0x3},
	{0xF8, 8, 0x3},
	{0xF8, 10, 0x3},
	{0xF8, 12, 0x3},
	{0xF8, 14, 0x3},
	{0xF8, 16, 0x3},
	{0xF8, 18, 0x3},
	{0xF8, 20, 0x3},
	{0xF8, 22, 0x3},
	{0xF8, 24, 0x3},
	{0xF8, 26, 0x3},
	{0xF8, 28, 0x3},
	{0xF8, 30, 0x3}, // gpio143

};
#define MCU_PIN_NUM		ARRAY_SIZE(amt630hv160_mcu_pin_map)

static const xPinGroup_t pin_groups[] = {
	{.groupid = PGRP_UART1, .pins_num = 2, .pins = {{67, 2}, {68, 2}}},
	{.groupid = PGRP_UART2, .pins_num = 2, .pins = {{69, 2}, {70, 2}}},
	{.groupid = PGRP_UART3, .pins_num = 2, .pins = {{71, 2}, {72, 2}}},
	{.groupid = PGRP_SDMMC1, .pins_num = 7, .pins = {{58, 2}, {59, 2}, {60, 2}, {61, 2}, {62, 2}, {63, 2},{64, 2}}},
	{.groupid = PGRP_ETH, .pins_num = 15, .pins = {
#if ETH_TXC_PAD_DIR_OUTPUT
					{0, 3}, 
#else
					{0, 2}, 
#endif
					{1, 2}, {2, 2}, {3, 2}, {4, 2}, {5, 2},{6, 2},
					{7, 2},{8, 2},{9, 2},{10, 2},{11, 2},{12, 2},{13, 2},{14, 2}}},
	{.groupid = PGRP_SPI1, .pins_num = 4, .pins = {{86, 1}, {87, 2}, {88, 2}, {89, 2}}},
	{.groupid = PGRP_SPI2, .pins_num = 6, .pins = {{80, 1}, {81, 2}, {82, 2}, {83, 2}, {84, 2}, {85, 2}}},
	{.groupid = PGRP_I2C0, .pins_num = 2, .pins = {{97, 2},{98, 2}}},
	{.groupid = PGRP_I2C1, .pins_num = 2, .pins = {{65, 2},{66, 2}}},

	{.groupid = PGRP_I2S1_PLAY, .pins_num = 5, .pins = {{75, 2}, {76, 2}, {77, 2}, {78, 2}, {79 ,2}},\
				.pin_mux_num = 1,.pin_mux = {\
					{.mux_reg = PINCTL_REG_BASE + 0xF4,.mux_offset = 6,.mux_mask = 0x3,.mux_val = 0x3}, // GPIO78 -> I2S1_OUT0
					}
	},
	{.groupid = PGRP_I2S1_RECORD, .pins_num = 5, .pins = {{75, 2}, {76, 2}, {77, 2}, {78, 2}, {79 ,2}},\
				.pin_mux_num = 2,.pin_mux = {\
					{.mux_reg = PINCTL_REG_BASE + 0xF4,.mux_offset = 7,.mux_mask = 0x1,.mux_val = 0x0}, //  i2s1_sdin_oe = 0
					{.mux_reg = PINCTL_REG_BASE + 0xF4,.mux_offset = 2,.mux_mask = 0x1,.mux_val = 0x1}, // i2s1_sadata_in sel = 1
					}
	},

	{.groupid = PGRP_RCRT, .pins_num = 1, .pins = {{96, 2}}},
	{.groupid = PGRP_PWM6, .pins_num = 1, .pins = {{90, 2}}},
	{.groupid = PGRP_PWM7, .pins_num = 1, .pins = {{91, 2}}},
	{.groupid = PGRP_PWM0_IN, .pins_num = 1, .pins = {{92, 2}}},
	{.groupid = PGRP_PWM1_IN, .pins_num = 1, .pins = {{93, 2}}},
	{.groupid = PGRP_PWM2_IN, .pins_num = 1, .pins = {{94, 2}}},
	{.groupid = PGRP_PWM3_IN, .pins_num = 1, .pins = {{95, 2}}},
	{.groupid = PGRP_ITU_CH0,.pins_num = 11, .pins = {{99,2},{100,2},{101,2},{102,2},{103,2},{104,2},{105,2},{106,2},{107,2},{108,2},{109,2}}},
	{.groupid = PGRP_ITU_CH0_MIPI,.pins_num = 11, .pins = {{99,1},{100,1},{101,1},{102,1},{103,1},{104,1},{105,1},{106,1},{107,1},{108,1},{109,1}}},
        

};
#define GROUP_NUM	ARRAY_SIZE(pin_groups)

static xPinGroup_t mcu_pin_groups[] = {
	{.groupid = PGRP_UART0, .pins_num = 2, .pins = {{74, 2}, {75, 2}}},
	{.groupid = PGRP_LCD_TTL_CH0, .pins_num = 28,
					/* de       clk      vynsc    hsync */
		.pins = {{54, 2}, {55, 2, PAD_DRIVE_4MA}, {56, 2}, {57, 2},
				 {40, 2}, {41, 2}, {42, 2}, {43, 2}, {44, 2}, {45, 2}, {46, 2}, {47, 2},
				 {101, 2}, {102, 2}, {48, 2}, {49, 2}, {50, 2}, {51, 2}, {52, 2}, {53, 2},
				 {103, 2}, {104, 2}, {105, 2}, {106, 2}, {107, 2}, {108, 2}, {109, 2}, {110, 2},}},
	{.groupid = PGRP_SPI0, .pins_num = 5, .pins = {{84, 2}, {85, 2}, {86, 2}, {87, 2}, {88, 2}}},
	{.groupid = PGRP_SDMMC0, .pins_num = 7, .pins = {{67, 2}, {68, 2}, {69, 2}, {70, 2}, {71, 2}, {72, 2}, {73, 2}},.pin_mux_num = 0},
	{.groupid = PGRP_I2S0_PLAY, .pins_num = 5, .pins = {{78, 2}, {79, 2}, {80, 2}, {81, 2}, {82, 2}},\
				.pin_mux_num = 1,.pin_mux = {\
					{.mux_reg = PINCTL_REG_BASE + 0xF4,.mux_offset = 4,.mux_mask = 0x3,.mux_val = 0x3}, // MCU-GPIO81 -> I2S0_OUT0
					}
	},
	{.groupid = PGRP_I2S0_RECORD, .pins_num = 5, .pins = {{78, 2}, {79, 2}, {80, 2}, {81, 2}, {82, 2}},\
				.pin_mux_num = 1,.pin_mux = {\
					{.mux_reg = PINCTL_REG_BASE + 0xF4,.mux_offset = 4,.mux_mask = 0x3,.mux_val = 0x0}, // MCU-GPIO81 -> I2S0_IN0
					}
	},
	{.groupid = PGRP_PWM0, .pins_num = 1, .pins = {{95, 2}}},
	{.groupid = PGRP_PWM1, .pins_num = 1, .pins = {{96, 2}}},
	{.groupid = PGRP_PWM2, .pins_num = 1, .pins = {{97, 2}}},
	{.groupid = PGRP_PWM3, .pins_num = 1, .pins = {{98, 2}}},
	{.groupid = PGRP_PWM4, .pins_num = 1, .pins = {{99, 2}}},
	{.groupid = PGRP_PWM5, .pins_num = 1, .pins = {{100, 2}}},
};
#define MCU_GROUP_NUM	ARRAY_SIZE(mcu_pin_groups)

static __INLINE void pinctrl_set_pin(int npin, int val, int drive)
{
	const xPinmap_t *pctrl;
	uint32_t reg;

	if (npin >= PIN_NUM)
		return;

	pctrl = &amt630hv160_pin_map[npin];

	reg = readl(PINCTL_REG_BASE + pctrl->reg);
	reg &= ~(pctrl->mask << pctrl->offset);
	reg |= val << pctrl->offset;
	writel(reg, PINCTL_REG_BASE + pctrl->reg);

	if (drive != PAD_DRIVE_DEFAULT) {
		uint32_t drv_reg = SYS_IO_DRIVER00 + pctrl->reg - SYS_PAD_CTRL00;
		vSysctlConfigure(drv_reg, pctrl->offset, 3, drive - 1);
	}
}

static __INLINE void mcu_pinctrl_set_pin(int npin, int val, int drive)
{
	const xPinmap_t *pctrl;
	uint32_t reg;

	if (npin >= MCU_PIN_NUM)
		return;

	pctrl = &amt630hv160_mcu_pin_map[npin];

	reg = readl(PINCTL_REG_BASE + pctrl->reg);
	reg &= ~(pctrl->mask << pctrl->offset);
	reg |= val << pctrl->offset;
	writel(reg, PINCTL_REG_BASE + pctrl->reg);

	if (drive != PAD_DRIVE_DEFAULT) {
		uint32_t drv_reg = SYS_IO_DRIVER00 + pctrl->reg - SYS_PAD_CTRL00;
		vSysctlConfigure(drv_reg, pctrl->offset, 3, drive - 1);
	}
}

void pinctrl_gpio_request(int gpio)
{
	pinctrl_set_pin(gpio, 1, PAD_DRIVE_DEFAULT);
}

void pinctrl_set_group(int groupid)
{
	int i, j;
	const xPinGroup_t *pgrp;
	uint32_t reg;

	for (i = 0; i < GROUP_NUM; i++) {
		pgrp = &pin_groups[i];
		if (pgrp->groupid == groupid) {
			configASSERT(pgrp->pins_num <= MAX_PINS_PER_GROUP);
			for (j = 0; j < pgrp->pins_num; j++){
				pinctrl_set_pin(pgrp->pins[j].muxio, pgrp->pins[j].pinval,
								pgrp->pins[j].drive);
			}

			configASSERT(pgrp->pin_mux_num <= MAX_PIN_MUX_GROUP);
			for(j = 0; j < pgrp->pin_mux_num; j++){
				if (pgrp->pin_mux[j].mux_reg) {
					reg = readl(pgrp->pin_mux[j].mux_reg);
					reg &= ~(pgrp->pin_mux[j].mux_mask << pgrp->pin_mux[j].mux_offset);
					reg |= pgrp->pin_mux[j].mux_val << pgrp->pin_mux[j].mux_offset;
					writel(reg, pgrp->pin_mux[j].mux_reg);
				}
			}

			break;
		}
	}
	for (i = 0; i < MCU_GROUP_NUM; i++) {
		pgrp = &mcu_pin_groups[i];
		if (pgrp->groupid == groupid) {
			configASSERT(pgrp->pins_num <= MAX_PINS_PER_GROUP);
			for (j = 0; j < pgrp->pins_num; j++){
				mcu_pinctrl_set_pin(pgrp->pins[j].muxio, pgrp->pins[j].pinval,
								pgrp->pins[j].drive);
			}

			configASSERT(pgrp->pin_mux_num <= MAX_PIN_MUX_GROUP);
			for(j = 0; j < pgrp->pin_mux_num; j++){
				if (pgrp->pin_mux[j].mux_reg) {
					reg = readl(pgrp->pin_mux[j].mux_reg);
					reg &= ~(pgrp->pin_mux[j].mux_mask << pgrp->pin_mux[j].mux_offset);
					reg |= pgrp->pin_mux[j].mux_val << pgrp->pin_mux[j].mux_offset;
					writel(reg, pgrp->pin_mux[j].mux_reg);
				}
			}

			break;
		}
	}
}

void vPinctrlSetup(void)
{
#ifdef SDMMC0_SUPPORT
	pinctrl_set_group(PGRP_SDMMC0);
#endif
#ifdef SDMMC1_SUPPORT
	pinctrl_set_group(PGRP_SDMMC1);
#endif


#ifdef DW_I2C0_SUPPORT
	pinctrl_set_group(PGRP_I2C0);
#endif
#ifdef DW_I2C1_SUPPORT
	pinctrl_set_group(PGRP_I2C1);
#endif


#ifdef PWM_CAP_SUPPORT
	pinctrl_set_group(PGRP_PWM2_IN);
#endif


#ifdef DW_SPI0_SUPPORT
	pinctrl_set_group(PGRP_SPI0);
#endif
#ifdef DW_SPI2_SUPPORT
	pinctrl_set_group(PGRP_SPI2);
#endif
#ifdef EC_SPI1_SUPPORT
	pinctrl_set_group(PGRP_SPI1);
#endif


#ifdef REMOTE_SUPPORT
	pinctrl_set_group(PGRP_RCRT);
#endif

#if LCD_INTERFACE_TYPE == LCD_INTERFACE_TTL
	pinctrl_set_group(PGRP_LCD_TTL_CH0);
#endif
        
#ifdef VIDEO_DECODER_MIPI	
	pinctrl_set_group(PGRP_ITU_CH0_MIPI);
#else
	pinctrl_set_group(PGRP_ITU_CH0);
#endif

#ifdef AUDIO_REPLAY
#if	(AUDIO_REPLAY_I2S == I2S_ID1)
	pinctrl_set_group(PGRP_I2S1_PLAY);
#else
	pinctrl_set_group(PGRP_I2S0_PLAY);
#endif
#endif

#ifdef AUDIO_RECORD
#if	(AUDIO_RECORD_I2S == I2S_ID1)
	pinctrl_set_group(PGRP_I2S1_RECORD);
#else
	pinctrl_set_group(PGRP_I2S0_RECORD);
#endif
#endif

	if(UART_DEBUG_PORT == UART_ID0)
		pinctrl_set_group(PGRP_UART0);
	else if (UART_DEBUG_PORT == UART_ID1)
		pinctrl_set_group(PGRP_UART1);
	else if (UART_DEBUG_PORT == UART_ID2)
		pinctrl_set_group(PGRP_UART2);
	else if (UART_DEBUG_PORT == UART_ID3)
		pinctrl_set_group(PGRP_UART3);
#ifdef ETH_SUPPORT
	pinctrl_set_group(PGRP_ETH);
#endif
}