#ifndef _SYSCTL_H
#define _SYSCTL_H

#ifdef __cplusplus
extern "C" {
#endif

#define SYS_BOOT_SAMPLE							0x0
#define SYS_CPUPLL_CFG							0X4
#define SYS_SYSPLL_CFG							0X8
#define SYS_DDRPLL_CFG							0xc
#define SYS_VPUPLL_CFG							0x10
#define SYS_MFCPLL_CFG							0X14
#define SYS_AHBPLL_CFG							0X18
#define SYS_GPUPLL_CFG							0X1C
#define SYS_SYSPLL_SPRD_CTL						0X20
#define SYS_AHBPLL_SPRD_CTL						0X24
#define SYS_VPUPLL_SPRD_CTL						0X28
#define SYS_WDTRST_REG							0X30
#define SYS_BUS_CLK_CFG							0x40
#define SYS_BUS_CLK1_CFG						0x180
#define SYS_PER_CLK_CFG							0x44
#define SYS_SDMMC_CLK_CFG						0x48
#define SYS_VOU_CLK_CFG							0x4c
#define SYS_BUS_CLK_EN							0x50
#define SYS_BUS_CLK_EN1							0x54
#define SYS_PER_CLK_EN							0x58
#define SYS_PER_CLK_EN1							0x184
#define SYS_SOFTRESET_CTL						0x5c
#define SYS_SOFTRESET_CTL1						0x60
#define SYS_SOFTRESET_CTL2						0x188
#define SYS_SSP_CLK_CFG							0x64
#define SYS_TIMER_CLK_CFG						0x68
#define SYS_I2S_NCO_CFG							0x6c
#define SYS_I2S_NCO_CFG1						0x18c
#define SYS_SDMMC1_CLK_CFG						0x70
#define SYS_DDR_CTL1_CFG						0X74
#define SYS_PERCTL_CFG							0x78
#define SYS_TIMER1_CLK_CFG						0x7c
#define SYS_ANA_CFG								0x80
#define SYS_ANA1_CFG							0x84
#define SYS_ANA2_CFG							0x88
#define SYS_ANA3_CFG							0x8c
#define SYS_ANA4_CFG							0x90
#define SYS_ANA5_CFG							0x94
#define SYS_ANA6_CFG							0x98
#define SYS_ANA8_CFG							0xA0
#define SYS_ADC_CLK1_CFG						0xA4

#define SYS_PAD_CTRL00							0xc0
#define SYS_PAD_CTRL01							0xc4
#define SYS_PAD_CTRL02							0xc8
#define SYS_PAD_CTRL03							0xcc
#define SYS_PAD_CTRL04							0xd0
#define SYS_PAD_CTRL05							0xd4
#define SYS_PAD_CTRL06							0xd8
#define SYS_PAD_CTRL07							0xdc
#define SYS_PAD_CTRL08							0xe0
#define SYS_PAD_CTRL09							0xe4
#define SYS_PAD_CTRL10							0xe8
#define SYS_PAD_CTRL11							0xec
#define SYS_PAD_CTRL12							0xf0
#define SYS_PAD_CTRL13							0xf4
#define SYS_PAD_CTRL14							0xf8

#define SYS_IO_DRIVER00							0x100
#define SYS_IO_DRIVER01							0x104
#define SYS_IO_DRIVER02							0x108
#define SYS_IO_DRIVER03							0x10c
#define SYS_IO_DRIVER04							0x110
#define SYS_IO_DRIVER05							0x114
#define SYS_IO_DRIVER06							0x118
#define SYS_IO_DRIVER07							0x11c
#define SYS_IO_DRIVER08							0x120
#define SYS_IO_DRIVER09							0x124
#define SYS_IO_DRIVER10							0x128
#define SYS_IO_DRIVER11							0x12c
#define SYS_IO_DRIVER14							0x138
#define SYS_IO_DRIVER15							0x13c

#define SYS_PAD_PUDCTL0							0x140
#define SYS_PAD_PUDCTL1							0x144
#define SYS_PAD_PUDCTL2							0x148
#define SYS_PAD_PUDCTL3							0x14c
#define SYS_PAD_PUDCTL4							0x150
#define SYS_PAD_PUDCTL5							0x154
#define SYS_PAD_PUDCTL6							0x158
#define SYS_PAD_PUDCTL7							0x15c
#define SYS_PAD_PUDCTL8							0x160
#define SYS_PAD_PUDCTL9							0x164
#define SYS_PAD_PUDCTL10						0x168
#define SYS_PAD_PUDCTL11						0x16c
#define SYS_PAD_PUDCTL13						0x174
#define SYS_PAD_PUDCTL14						0x178

#define SYS_MIPI_CTL							0X190
#define SYS_MIPI_BIST							0X194
#define SYS_MIPI_CLK_CFG						0X198
#define SYS_MIPI_CSI_CFG1						0X19C
#define SYS_MIPI_CSI_CFG2						0X1A0
#define SYS_MIPI_CSI_CFG3						0X1A4
#define SYS_MIPI_CSI_CFG4						0X1A8
#define SYS_GBUS_PRIORITY						0X1AC
#define SYS_CHBUS_PRIORITY						0X1B0

#define SYS_MIPI_TEST_CTL						0X1C0
#define SYS_MIPI_TEST_CTL1						0X1C4
#define SYS_WRAP_CFG							0X1C8
#define SYS_RDC_CFG								0X200


enum soft_rst_n{
	// SOF_RST_CTL0
	softreset_sdmmc1	=	(32*0+31),
	softreset_i2s1		=	(32*0+30),
	softreset_qoi_core	=	(32*0+29),
	softreset_qoi		=	(32*0+28),

	softreset_rcrt      =	(32*0+26),
	softreset_adc       =	(32*0+25),
	softreset_rtc       =	(32*0+24),
	softreset_i2s       =	(32*0+23),
	softreset_wdt       =	(32*0+22),
	softreset_pwm       =	(32*0+21),
	softreset_timer3    =	(32*0+20),
	softreset_timer2    =	(32*0+19),
	softreset_timer1    =	(32*0+18),
	softreset_timer0    =	(32*0+17),
	softreset_gpio      =	(32*0+16),
	softreset_uart3     =	(32*0+15),
	softreset_uart2     =	(32*0+14),
	softreset_uart1     =	(32*0+13),
	softreset_uart0     =	(32*0+12),
	softreset_i2c1      =	(32*0+11),
	softreset_i2c       =	(32*0+10),
	softreset_ssp1      =	(32*0+9),
	softreset_ssp0       =	(32*0+8),
	softreset_gpu_core  =	(32*0+7),
	softreset_gpu       =	(32*0+6),
	softreset_itu       =	(32*0+5),
	softreset_sdmmc     =	(32*0+4),
	softreset_usb       =	(32*0+3),
	softreset_pxp       =	(32*0+2),
	softreset_dma       =	(32*0+1),
	softreset_lcd       =	(32*0+0),

	// SOF_RST_CTL1
	softreset_cabuspclk =	(32*1+31),
	softreset_chbuspclk =	(32*1+30),
	softreset_gbuspclk	=	(32*1+29),
	softreset_mailbox 	=	(32*1+28),
	softreset_sema	 	=	(32*1+27),
	softreset_crc	 	=	(32*1+26),
	softreset_buspclk 	=	(32*1+25),
	softreset_adc1		=	(32*1+24),
	softreset_cpu_cnt	=	(32*1+23),
	softreset_usbphy	=	(32*1+22),
	softreset_ddrphy	=	(32*1+21),
	softreset_ddrctl	=	(32*1+20),
	softreset_ddr3		=	(32*1+19),
	softreset_ddr2		=	(32*1+18),
	softreset_ddr1		=	(32*1+17),
	softreset_ddr0		=	(32*1+16),
	softreset_codec		=	(32*1+7),
	softreset_eth		=	(32*1+6),
	softreset_utmi		=	(32*1+5),
	softreset_ble		=	(32*1+4),
	softreset_h2xusb	=	(32*1+3),
	softreset_h2xdma	=	(32*1+2),
	softreset_ssp2		=	(32*1+1),
	softreset_mfc		=	(32*1+0),

	// SOF_RST_CTL2
	softreset_csi_pix2xclk	=	(32*2+6),
	softreset_csi_pixclk	=	(32*2+5),
	softreset_wrap_sram		=	(32*2+4),
	softreset_wrap			=	(32*2+3),
	softreset_adc2			=	(32*2+2),
	softreset_csi			=	(32*2+1),
	softreset_dsi			=	(32*2+0),
};


extern void vSysctlConfigure(uint32_t regoffset, uint32_t bitoffset, uint32_t mask, uint32_t val);

extern void sys_soft_reset (enum soft_rst_n reset_dev);

extern void sys_soft_reset_from_isr (enum soft_rst_n reset_dev);

#ifdef __cplusplus
}
#endif

#endif