main.c 6.2 KB

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  1. /*******************************************************************************
  2. * File Name : main.c
  3. * Author : Sim
  4. * Date First Issued : 12/28/2022
  5. * Description : application entry
  6. ********************************************************************************
  7. * History:
  8. * 12/28/2022: V0.1
  9. *******************************************************************************/
  10. /* Includes ------------------------------------------------------------------*/
  11. #include <stdio.h>
  12. #include <string.h>
  13. #include <intrinsics.h>
  14. #include "mpu_demo.h"
  15. #include "sfud.h"
  16. #include "amt630hv160_lib.h"
  17. #include "update.h"
  18. #include "secure_funcs.h"
  19. #include "fs/ff.h"
  20. #include "fs/diskio.h"
  21. #include "libhsm.h"
  22. #include "mailbox_message.h"
  23. #include "access_module.h"
  24. #if ADC_DEMO
  25. extern void adc_demo(void);
  26. #endif
  27. #ifdef MEDIA_UPDATE_SUPPORT
  28. extern void MediaUpdateReceiveDemo(void);
  29. #endif
  30. extern void StartCpu(void);
  31. extern void can_ecu_demo(void);
  32. extern void can_host_demo(void);
  33. #if RTC_DEMO
  34. extern void rtc_sleep_demo(void);
  35. extern void rtc_wakeup_demo(void);
  36. #endif
  37. void SystemInit(void)
  38. {
  39. /* disable systick */
  40. *(volatile u32*)SysTick_BASE = 0;
  41. #ifndef DEBUG
  42. NVIC_DeInit();
  43. #endif
  44. }
  45. static void prvSetupHardware( void )
  46. {
  47. /* Set the Vector Table base address at 0x20100000 */
  48. NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
  49. NVIC_PriorityGroupConfig(NVIC_PriorityGroup_6);
  50. __set_BASEPRI( 0 ); //ENABLE GLOBAL IRQ
  51. /* Configure the regions in the MPU that are common to all tasks. */
  52. prvSetupMPU();
  53. /* Init sema. */
  54. sema_init();
  55. /* Init Delay Timer. */
  56. TIMER_InitForDelay();
  57. /* Init Debug Uart */
  58. UART_Init(PRINT_UART, 115200, 0);
  59. /* Config the Clock */
  60. SYSCLK_Init();
  61. printf("sys_pll=%d\n", CLK_GetPLLFreq(SYSCTRL->SYSPLL_CFG));
  62. printf("cpu_pll=%d\n", CLK_GetPLLFreq(SYSCTRL->CPUPLL_CFG));
  63. printf("vpu_pll=%d\n", CLK_GetPLLFreq(SYSCTRL->VPUPLL_CFG));
  64. printf("ddr_pll=%d\n", CLK_GetPLLFreq(SYSCTRL->DDRPLL_CFG));
  65. printf("mfc_pll=%d\n", CLK_GetPLLFreq(SYSCTRL->MFCPLL_CFG));
  66. printf("ahb_pll=%d\n", CLK_GetPLLFreq(SYSCTRL->AHBPLL_CFG));
  67. printf("gpu_pll=%d\n", CLK_GetPLLFreq(SYSCTRL->GPUPLL_CFG));
  68. #ifdef _RTC
  69. RTC_SendCmd(RTC_Clk32KSel, 1);
  70. //rtc_time_init();
  71. #endif
  72. #ifdef _SPI0
  73. SPI0_SetBusClk(SPI0_FREQ);
  74. SPI0_SelectPad();
  75. #endif
  76. #ifdef _SDMMC0
  77. SDMMC0_SetBusClk(SDMMC0_FREQ);
  78. SDMMC0_SelectPad();
  79. #endif
  80. #ifdef _SDMMC1
  81. SDMMC1_SetBusClk(SDMMC1_FREQ);
  82. SDMMC1_SelectPad();
  83. #endif
  84. #ifdef _CANFD0
  85. CANFD0_SetBusClk(CANFD0_FREQ);
  86. #endif
  87. #ifdef _CANFD1
  88. CANFD1_SetBusClk(CANFD1_FREQ);
  89. #endif
  90. #ifndef SYSTICK_TIMER
  91. /* Configure HCLK clock as SysTick clock source. */
  92. SysTick_CLKSourceConfig( SysTick_CLKSource_CORECLK );
  93. #endif
  94. #ifdef _DMA
  95. DMA_Init();
  96. #endif
  97. #ifdef _SPI0
  98. dwspi_init();
  99. #endif
  100. #ifdef _I2C0
  101. i2c_dw_init(I2C_ID0);
  102. #endif
  103. #ifdef _I2C1
  104. i2c_dw_init(I2C_ID1);
  105. #endif
  106. #ifdef _MAILBOX
  107. mailbox_msg_init();
  108. #endif
  109. #ifdef _MCU_WDT
  110. WDT_Init();
  111. #endif
  112. #ifdef _ADC
  113. adc_hardware_init();
  114. #endif
  115. #ifdef _MCU_GPIO
  116. GPIO_IrqRegister();
  117. #endif
  118. #ifdef _RTC
  119. RTC_WakeupDetect();
  120. #if RTC_DEMO
  121. rtc_wakeup_demo();
  122. #endif
  123. #endif
  124. }
  125. int LoadFastboot(void)
  126. {
  127. header_offset_t *hoff = GetHeaderOff();
  128. u8 *buf = (u8*)MCU_IRAM_BASE;
  129. if ((hoff->fboffset == FASTBOOTA_OFFSET
  130. || hoff->fboffset == FASTBOOTB_OFFSET)
  131. && hoff->fbsize <= FASTBOOT_MAX_SIZE) {
  132. UPDATE_ReadData(hoff->fboffset, buf, hoff->fbsize);
  133. if (xcrc32((void*)buf, hoff->fbsize, 0xffffffff, HARD_CALC_CRC) != hoff->fbcrc) {
  134. TRACE_ERROR("Load fastboot checksum fail!\n");
  135. return -1;
  136. }
  137. return 0;
  138. }
  139. return -1;
  140. }
  141. int main(void)
  142. {
  143. #ifdef DEBUG
  144. debug();
  145. //disable interrupt
  146. NVIC_DeInit();
  147. #endif
  148. //1.8V低电压复位
  149. //LPR_TH 00:<1.45V 01:<1.41V 10:<1.38V 11:<1.35V
  150. SYSCTRL->ANA_REG[0] &= ~7;
  151. /*LPR_TH*/ /*LPR_EN*/
  152. SYSCTRL->ANA_REG[0] |= (0x3 << 1) | 1;
  153. //disable ecc error reset
  154. MCU_SYSCTRL->V6_RST_CTL &= ~(1UL << 31);
  155. prvSetupHardware();
  156. printf("amthv160 app %s %s\n", __DATE__, __TIME__);
  157. #if DEVICE_TYPE_SELECT != EMMC_FLASH
  158. #ifdef SPI0_QSPI_MODE
  159. sfud_flash *sflash;
  160. sfud_err result;
  161. u8 status;
  162. u8 qe_wsta_cmd = 0;
  163. u8 qe_sta_bit = 0;
  164. #endif
  165. if (sfud_init()) {
  166. printf("sfud_init fail!\n");
  167. while(1);
  168. }
  169. #ifdef SPI0_QSPI_MODE
  170. sflash = sfud_get_device(0);
  171. switch (sflash->chip.mf_id) {
  172. case SFUD_MF_ID_WINBOND:
  173. case SFUD_MF_ID_GIGADEVICE:
  174. qe_wsta_cmd = 0x31;
  175. qe_sta_bit = 1;
  176. break;
  177. default:
  178. break;
  179. }
  180. if(qe_wsta_cmd | qe_sta_bit) {
  181. //Write QE
  182. result = sfud_read_status(sflash, &status, qe_wsta_cmd | (1 << 2));
  183. if (result != SFUD_SUCCESS) {
  184. printf("sfud read QE status register fail\n");
  185. while(1);
  186. }
  187. if (!(status & (1 << qe_sta_bit))) {
  188. status |= (1 << qe_sta_bit);
  189. sfud_write_status(sflash, false, status, qe_wsta_cmd);
  190. if (result != SFUD_SUCCESS) {
  191. printf("sfud write QE status register fail\n");
  192. while(1);
  193. }
  194. }
  195. }
  196. sfud_qspi_fast_read_enable(sflash, 4);
  197. #endif
  198. #else
  199. if (EMMC_Init()) {
  200. printf("EMMC_Init fail!\n");
  201. while(1);
  202. }
  203. EMMC_SetBusWidth(4);
  204. #endif
  205. ReadHeaderOff();
  206. secure_module_init();
  207. #if CAN_DEMO
  208. RTC_CanStbOut(0, 0);
  209. RTC_CanStbOut(1, 0);
  210. #else
  211. UPDATE_ReadImageHeader();
  212. ReadSysInfo();
  213. StartCpu();
  214. #if ADC_DEMO
  215. adc_demo();
  216. #endif
  217. #endif
  218. #if RTC_DEMO
  219. rtc_sleep_demo();
  220. #endif
  221. for (;;) {
  222. #if CAN_DEMO
  223. #if CAN_DEMO == CAN_ECU_DEMO
  224. can_ecu_demo();
  225. #elif CAN_DEMO == CAN_HOST_DEMO
  226. can_host_demo();
  227. #endif
  228. #else
  229. RebootCpu();
  230. #ifdef MEDIA_UPDATE_SUPPORT
  231. MediaUpdateReceiveDemo();
  232. #endif
  233. #ifdef CPU_ACCESS_MODULE_SUPPORT
  234. DetectCpuAccessModule();
  235. #endif
  236. #if defined(_UART0)
  237. if(PRINT_UART != UART0)
  238. uart_demo(UART_ID0);
  239. #endif
  240. #if defined(_UART1)
  241. if(PRINT_UART != UART1)
  242. uart_demo(UART_ID1);
  243. #endif
  244. #endif
  245. }
  246. }
  247. #ifdef DEBUG
  248. /* Keep the linker happy. */
  249. void assert_failed( unsigned char* pcFile, unsigned long ulLine )
  250. {
  251. for( ;; )
  252. {
  253. }
  254. }
  255. #endif
  256. void HardFault_Handler(void)
  257. {
  258. u32 pc;
  259. u32 sp = 0;
  260. //xPSR, pc, lr, r12, r3, r2, r1, r0
  261. asm("mov %0, sp" : : "r"(sp));
  262. pc = *(volatile u32*)(sp + 0x20);
  263. printf("hardfault addr 0x%x\n", pc);
  264. while (1);
  265. }
  266. void vApplicationMallocFailedHook( void )
  267. {
  268. /* If configUSE_MALLOC_FAILED_HOOK is set to 1 then this function will
  269. be called automatically if a call to pvPortMalloc() fails. pvPortMalloc()
  270. is called automatically when a task, queue or semaphore is created. */
  271. for( ;; );
  272. }
  273. /*-----------------------------------------------------------*/