amt630hv160-sdk-release/amt630hv160-freertos-beta/ArkmicroFiles/libcpu-amt630hv160/include/i2s.h

/*******************************************************************************
* File Name          : i2s.h
* Author             : ZJH
* Date First Issued  : 6/24/2024
* Description        : i2s drive.
********************************************************************************
* History:
* 6/24/2024: V0.1
*******************************************************************************/

#ifndef __ARK_I2S_H
#define __ARK_I2S_H

/*
 * I2S Controller Register and Bit Definitions
 */
#define I2S_SACR0			0x00  /* Global Control Register */
#define I2S_SACR1			0x04  /* Serial Audio I 2 S/MSB-Justified Control Register */
#define I2S_DACR0			0x08

#define I2S_WRCTL			0x08

#define I2S_RDCTL			0x10
#define I2S_SASR0			0x0C  /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
#define I2S_SAIMR			0x14  /* Serial Audio Interrupt Mask Register */
#define I2S_SAICR			0x18  /* Serial Audio Interrupt Clear Register */
#define I2S_ADCR0			0x1c
#define I2S_SADR			0x80  /* Serial Audio Data Register (TX and RX FIFO access Register). */

#define SACR0_RFIFIFIRSTBIT	(1 << 26)	/* rx fifo first bit */
#define SACR0_TFIFOFIRSTBIT	(1 << 25)	/* Tx fifo first bit */
#define SACR0_CHANLOCK		(1 << 24)	/* Channel lock(left first or right first) */
#define SACR0_SCBIT			(1 << 23)	/*  */
#define SACR0_BITS			(1 << 22)	/* I2S Bit Select(16/32 bits) */
#define SACR0_SYNCINV		(1 << 21)	/* SYNC Clock Invert */
#define SACR0_RFTH_MASK		(0x1F << 16)
#define SACR0_RFTH(x)		((x) << 16)	/* Rx FIFO Interrupt or DMA Trigger Threshold */
#define SACR0_TFTH_MASK		(0X1F << 8)
#define SACR0_TFTH(x)		((x) << 8)	/* Tx FIFO Interrupt or DMA Trigger Threshold */
#define SACR0_STRF			(1 << 7)	/* DAC output clk edge select */
#define SACR0_RDMAEN		(1 << 6)	/* RX DMA Enable */
#define SACR0_ENLBF			(1 << 5)	/* Enable Loopback */
#define SACR0_RST			(1 << 4)	/* FIFO, i2s Register Reset */
#define SACR0_TDMAEN		(1 << 3)	/* TX DMA Enable */
#define SACR0_BCKD			(1 << 2)	/* Bit Clock Direction */
#define SACR0_SYNCD			(1 << 1)	/* Word Select(sync) Clock Direction */
#define SACR0_ENB			(1 << 0)	/* Enable I2S Link */

#define SACR1_DRPL			(1 << 1)	/* Disable Replaying Function */
#define SACR1_DREC			(1 << 0)	/* Disable Recording Function */

#define SASR0_RFL(x) 		((x) << 16) /* Rx FIFO Level */
#define SASR0_TFL(x) 		((x) << 8) 	/* Tx FIFO Level */
#define SASR0_ROR			(1 << 6)	/* Rx FIFO Overrun */
#define SASR0_TUR			(1 << 5)	/* Tx FIFO Underrun */
#define SASR0_RFS			(1 << 4)	/* Rx FIFO Service Request */
#define SASR0_TFS			(1 << 3)	/* Tx FIFO Service Request */
#define SASR0_BSY			(1 << 2)	/* I2S Busy */
#define SASR0_RNE			(1 << 1)	/* Rx FIFO Not Empty */
#define SASR0_TNF			(1 << 0)	/* Tx FIFO Not Full */

#define SAICR_ROR			(1 << 6)	/* Clear Rx FIFO Overrun Interrupt */
#define SAICR_TUR			(1 << 5)	/* Clear Tx FIFO Underrun Interrupt */
#define SAICR_RFS			(1 << 4)	/* Clear Rx FIFO Service Interrupt */
#define SAICR_TFS			(1 << 3)	/* Clear Tx FIFO Service Interrupt */

#define SAIMR_ROR			(1 << 6)	/* Enable Rx FIFO Overrun Condition Interrupt */
#define SAIMR_TUR			(1 << 5)	/* Enable Tx FIFO Underrun Condition Interrupt */
#define SAIMR_RFS			(1 << 4)	/* Enable Rx FIFO Service Interrupt */
#define SAIMR_TFS			(1 << 3)	/* Enable Tx FIFO Service Interrupt */

#define I2S_SUP_MASTER			(1 << 0)
#define I2S_SUP_SLAVER			(1 << 1)
#define I2S_SUP_OUTPUT			(1 << 2)
#define I2S_SUP_INPUT			(1 << 3)
#define I2S_SUP_FULL_DUPLEX		(1 << 4)

#define I2S_DIR_OUTPUT			(1 << 0)
#define I2S_DIR_INPUT			(1 << 1)
#define I2S_DIR_FULL_DUPLEX 	(I2S_DIR_OUTPUT | I2S_DIR_INPUT)

#define I2S_VOL_MAX				AUDIO_VOLUME_MAX
#define I2S_VOL_MIN				AUDIO_VOLUME_MIN

#define I2S_STA_OUTPUTTING		(1 << 0)
#define I2S_STA_INPUTTING		(1 << 1)

enum i2s_type{
	IIS_BUS,
};

struct ark_i2s_cfg {
	uint8_t dir;
    int rates;
    uint8_t bits;
    int channels;
    uint8_t in_lvol;
    uint8_t in_rvol;
    uint8_t out_lvol;
    uint8_t out_rvol;
    uint8_t status;
    uint8_t rfirst;
};

struct ark_i2s_drv {
	uint32_t id;
	uint32_t base;
	uint32_t nco_base;
	uint32_t irqn;
	uint32_t dma_tx_req_id;
	uint32_t dma_rx_req_id;
	uint32_t clkid;
	uint32_t sup_func;
	uint32_t chn_sum;
	uint32_t softreset_id;
	uint32_t is_master;
	uint32_t dma_tx_chn;
	uint32_t dma_rx_chn;
	enum i2s_type type;
	struct dma_chan *dma_txch;
	struct dma_chan *dma_rxch;
	struct ark_i2s_cfg *cfg;
	const char *decoder_name;
	const char *encoder_name;
	void *extdata;
};

int ark_i2s_init(struct ark_i2s_drv *i2s, int dir);
int ark_i2s_set_samplerate(struct ark_i2s_drv *i2s, int rates);
int ark_i2s_set_channels(struct ark_i2s_drv *i2s, int channels);
int ark_i2s_set_samplebits(struct ark_i2s_drv *i2s, int bits);
int ark_i2s_set_rfirst(struct ark_i2s_drv *i2s, int enable);
int ark_i2s_set_volume(struct ark_i2s_drv *i2s, int dir, int lvol, int rvol);
int ark_i2s_set_mute(struct ark_i2s_drv *i2s, int dir, int mute);
int ark_i2s_startup(struct ark_i2s_drv *i2s, int dir);
int ark_i2s_stop(struct ark_i2s_drv *i2s, int dir);

#endif