amt630hv160-sdk-release/amt630hv160-freertos-beta/ArkmicroFiles/libcpu-amt630hv160/source/pwm_cap.c

#include "FreeRTOS.h"
#include "board.h"

#ifdef PWM_CAP_SUPPORT
#include "chip.h"
#include "pwm_cap.h"

#define PWM_CAP_INT_CLEAR       (0x10*4)
#define PWM_CAP_INT_EN          (0x20*4)
#define PWM_CAP_INT_STA         (0x21*4)

#define PWM_CAP_SYS_FRQ			(0x00)
#define PWM_CAP_SETTING			(0x04)
#define PWM_CAP_CYCLE_CAP		(0x08)
#define PWM_FRE_CAP				(0x0c)

#define PWM_CAP_REG(x)			(REGS_PWM_BASE + 0x100 + 0x10 * (x))

void pwm_cap_Int_Handler(void *para);

static void pwm_cap_clk_config(UINT8 id,UINT32 clk)
{
	writel(clk,PWM_CAP_REG(id) + PWM_CAP_SYS_FRQ);
}

static void pwm_cap_en(UINT8 id,UINT8 enable)
{
	unsigned int reg;
	reg = readl(PWM_CAP_REG(id) + PWM_CAP_SETTING);
	if(enable)
		reg |= (1UL<<31);
	else
		reg &= ~(1UL<<31);
	writel(reg, PWM_CAP_REG(id) + PWM_CAP_SETTING);
}

static void pwm_cap_int_method(UINT8 id,UINT8 int_method)
{
	unsigned int reg;
	reg = readl(PWM_CAP_REG(id) + PWM_CAP_SETTING);
	reg &= ~(0x3<<28);
	reg |= (int_method<<28);
	writel(reg,PWM_CAP_REG(id) + PWM_CAP_SETTING);
}

static void pwm_cap_set_glitch(UINT8 id,UINT8 glitch)
{
	unsigned int reg;
	reg = readl(PWM_CAP_REG(id) + PWM_CAP_SETTING);
	reg &= ~(0xF<<24);
	reg |= (glitch<<24);
	writel(reg,PWM_CAP_REG(id) + PWM_CAP_SETTING);
}

static void pwm_cap_method(UINT8 id,UINT8 cap_method)
{
	unsigned int reg;
	reg = readl(PWM_CAP_REG(id) + PWM_CAP_SETTING);
	reg &= ~(0x1<<30);
	reg |= (cap_method<<30);
	writel(reg,PWM_CAP_REG(id) + PWM_CAP_SETTING);
}

static void pwm_cap_times(UINT8 id,UINT8 cat_times)
{
	unsigned int reg;
	reg = readl(PWM_CAP_REG(id) + PWM_CAP_SETTING);
	reg &= ~(0xFF<<16);
	reg |= (cat_times<<16);
	writel(reg,PWM_CAP_REG(id) + PWM_CAP_SETTING);
}

static void pwm_cap_based_unit(UINT8 id,UINT8 cap_based_unit)
{
	unsigned int reg;
	reg = readl(PWM_CAP_REG(id) + PWM_CAP_SETTING);
	reg &= ~(0x7<<12);
	reg |= (cap_based_unit<<12);
	writel(reg,PWM_CAP_REG(id) + PWM_CAP_SETTING);
}

static void pwm_cap_interval(UINT8 id,UINT8 cap_interval)
{
	unsigned int reg;
	reg = readl(PWM_CAP_REG(id) + PWM_CAP_SETTING);
	reg &= ~(0xFF<<0);
	reg |= (cap_interval<<0);
	writel(reg,PWM_CAP_REG(id) + PWM_CAP_SETTING);
}

void pwm_Initial_Cap(UINT8 id)
{
	pwm_cap_clk_config(id,ulClkGetRate(CLK_APB));
	pwm_cap_int_method(id,PWM_CAP_ONCE_FINISH_INT);
	pwm_cap_set_glitch(id,PWM_CAP_GLITCH);
	pwm_cap_method(id,PWM_CAP_NUM);
	pwm_cap_times(id,PWM_CAP_TIMES);
	pwm_cap_based_unit(id,PWM_CAP_UINT_1000MS);
	pwm_cap_interval(id,PWM_CAP_INTERVAL);
	request_irq(PWM_IRQn, 0, pwm_cap_Int_Handler, NULL);
}

void pwm_cap_Int_Handler(void *param)
{
	int i;
	unsigned int val;

	val = readl(PWM_CAP_REG(PWM_CAP_CH0) + PWM_CAP_INT_STA);

	for(i=0; i<=PWM_CAP_CH3; i++){

		if(val & (1 << i)){
			printf("pwm cap[%d] interrupt!\n",i);
			writel(1 << i,PWM_CAP_REG(PWM_CAP_CH0) +PWM_CAP_INT_CLEAR);

			pwm_getCapVal(i);
			writel(0,PWM_CAP_REG(PWM_CAP_CH0) +PWM_CAP_INT_CLEAR);
			writel(readl(PWM_CAP_REG(i)+PWM_CAP_SETTING)|(1UL<<31), PWM_CAP_REG(i)+PWM_CAP_SETTING);
		}
	}
}

double pwm_getCapVal(UINT8 id)
{

	printf("pwmin chn:%d fre:%d \n", id, readl(PWM_CAP_REG(id)+PWM_FRE_CAP)/16);
	return (double)readl(PWM_CAP_REG(id)+PWM_FRE_CAP)/16;
}

void pwm_enableCapIRQ(UINT8 id,unsigned char en)
{
	unsigned int reg = 0;
	reg = readl(PWM_CAP_REG(0)+ PWM_CAP_INT_EN);
	reg &=~(1<<id);
	if(en)
	{
		reg |=(1<<id);
		writel(reg,PWM_CAP_REG(0)+ PWM_CAP_INT_EN);
	}
	else
	  	writel(reg,PWM_CAP_REG(0)+ PWM_CAP_INT_EN);
}

void pwm_cap_init(UINT8 id)
{
//	unsigned int irq_enable = 1;

	pwm_Initial_Cap(id);
	pwm_enableCapIRQ(id,1);
	pwm_cap_en(id,PWM_CAP_ENABLE);
}
#endif