// SPDX-License-Identifier: GPL-2.0
#include "skeleton.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/ark-clk.h>

/ {
	model = "ARM Arkmicro ark1668ed SoC";
	compatible = "arkmicro,ark1668ed";

	interrupt-parent = <&gic>;

	aliases {
		serial0 = &uart0;
//		hsserial0 = &uart4;
//		hsserial1 = &uart5;
	};

	chosen {
		bootargs = "console=ttyS0,115200 earlyprintk loglevel=8 clk_ignore_unused";
		stdout-path = "serial0:115200n8";
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "arkmicro,arke-smp";

		cpu0: cpu@0 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0>;
			clock-frequency = <800000000>;
			next-level-cache = <&L2_CA7>;
		};

		cpu1: cpu@1 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <1>;
			clock-frequency = <800000000>;
			next-level-cache = <&L2_CA7>;
		};

		L2_CA7: cache-controller-0 {
			compatible = "cache";
			cache-unified;
			cache-level = <2>;
		};
	};

	memory {
		reg = <0x60000000 0x1c000000>;
	};

	reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		/* global autoconfigured region for contiguous allocations */
		linux,cma {
			compatible = "shared-dma-pool";
			reusable;
			size = <0xc000000>;
			linux,cma-default;
		};
	};

	iram {
		compatible = "arkmicro,arke-iram";
		reg = <0x300000 0x8000>;
		cpuctlofset = <0x34>;
		enablebit = <0x0>;
	};

	timer {
		compatible = "arm,armv7-timer";
		arm,cpu-registers-not-fw-configured;
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
		clock-frequency = <24000000>;
	};

	sregs@50000000 {
		compatible = "arkmicro,ark-sregs";
		reg = <0x50000000 0x1000>;

		clocks {
			#address-cells = <1>;
			#size-cells = <0>;

			xtal32k: xtal32k@32K {
				#clock-cells = <0>;
				compatible = "fixed-clock";
				clock-frequency = <32768>;
			};

			xtal24mhz: xtal24mhz@24M {
				#clock-cells = <0>;
				compatible = "fixed-clock";
				clock-frequency = <24000000>;
			};

			clk24mhz: clk24mhz@24M {
				#clock-cells = <0>;
				compatible = "fixed-clock";
				clock-frequency = <24000000>;
			};
			xtal25mhz: xtal25mhz@25M {
				#clock-cells = <0>;
				compatible = "fixed-clock";
				clock-frequency = <25000000>;
			};

			clk240mhz: clk240mhz@240M {
				#clock-cells = <0>;
				compatible = "fixed-factor-clock";
				clock-div = <1>;
				clock-mult = <10>;
				clocks = <&xtal24mhz>;
			};

			clk12mhz: clk12mhz@12M {
				#clock-cells = <0>;
				compatible = "fixed-factor-clock";
				clock-div = <2>;
				clock-mult = <1>;
				clocks = <&xtal24mhz>;
			};

			clk6mhz: clk6mhz@6M {
				#clock-cells = <0>;
				compatible = "fixed-factor-clock";
				clock-div = <4>;
				clock-mult = <1>;
				clocks = <&xtal24mhz>;
			};

			cpupll: cpupll {
				#clock-cells = <0>;
				compatible = "arkmiro,arked-clk-pll";
				clocks = <&xtal24mhz>;
				reg = <0x04>;
				};
			dsppll: dsppll {
				#clock-cells = <0>;
				compatible = "arkmiro,arked-clk-pll";
				clocks = <&xtal24mhz>;
				reg = <0x08>;
				};

			syspll: syspll {
				#clock-cells = <0>;
				compatible = "arkmiro,arked-clk-pll";
				clocks = <&xtal24mhz>;
				reg = <0x0c>;

				};

			ddrpll: ddrpll {
				#clock-cells = <0>;
				compatible = "arkmiro,arked-clk-pll";
				clocks = <&xtal24mhz>;
				reg = <0x10>;

				};

			vpupll: vpupll {
				#clock-cells = <0>;
				compatible = "arkmiro,arked-clk-pll";
				clocks = <&xtal24mhz>;
				reg = <0x14>;

				};


			mfcpll: mfcpll {
				#clock-cells = <0>;
				compatible = "arkmiro,arked-clk-pll";
				clocks = <&xtal24mhz>;
				reg = <0x18>;

			};

			ahbpll: ahbpll {
				#clock-cells = <0>;
				compatible = "arkmiro,arked-clk-pll";
				clocks = <&xtal24mhz>;
				reg = <0x1c>;

			};

			gpupll: gpupll {
				#clock-cells = <0>;
				compatible = "arkmiro,arked-clk-pll";
				clocks = <&xtal24mhz>;
				reg = <0x20>;

			};

			tvpll: tvpll {
				#clock-cells = <0>;
				compatible = "arkmiro,arked-clk-pll";
				clocks = <&xtal24mhz>;
				reg = <0x24>;

			};
			pclk: pclk {
				#clock-cells = <0>;
				compatible = "arkmiro,ark-clk-sys";
				clocks = <&xtal24mhz>,<&ahbpll>;
				reg = <0x40>;
				index-offset = <3>;
				index-mask = <0x1>;
				index-value = <1>;
				div-offset = <4>;
				div-mask = <0x3>;
				div-value = <2>;
				div-mode = <ARK_CLK_DIVMODE_EXPONENT>;
			};

			pwmclk: pwmclk {
				#clock-cells = <0>;
				compatible = "arkmiro,ark-clk-sys";
				clocks = <&xtal24mhz>;
				reg = <0x60>;
				index-offset = <8>;
				index-mask = <0x1>;
				index-value = <0>;
				div-offset = <4>;
				div-mask = <0xf>;
				div-value = <1>;
				div-mode = <ARK_CLK_DIVMODE_NOZERO>;
				enable-reg = <0x48 0x50>;
				enable-offset = <13 27>;
				status = "disabled";

			};

			rtc_clk: rtc-clk {
				#clock-cells = <0>;
				compatible = "arkmiro,ark-clk-sys";
				clocks = <&xtal32k>;
				reg = <0x48>;
				enable-reg = <0x48>;
				enable-offset = <6>;
				status = "disabled";
			};

			ssi_clk: ssi-clk {
				#clock-cells = <0>;
				compatible = "arkmiro,ark-clk-sys";
				clocks = <&ahbpll>, <&xtal24mhz>;
				reg = <0x60>;
				index-offset = <20>;
				index-mask = <0xf>;
				index-value = <1>;
				div-offset = <16>;
				div-mask = <0xf>;
				div-value = <6>;
				div-mode = <ARK_CLK_DIVMODE_PONEDOUBLE>;
				enable-reg = <0x48 0x50>;
				enable-offset = <4 13>;
				status = "disabled";
			};

			spi_clk: spi-clk {
				#clock-cells = <0>;
				compatible = "arkmiro,ark-clk-sys";
				clocks = <&ahbpll>, <&xtal24mhz>;
				reg = <0x228>;
				index-offset = <4>;
				index-mask = <0xf>;
				index-value = <1>;
				div-offset = <0>;
				div-mask = <0xf>;
				div-value = <6>;
				div-mode = <ARK_CLK_DIVMODE_PONEDOUBLE>;
				enable-reg = <0x48>;
				enable-offset = <24>;
				status = "disabled";
			};

			mmc0clk: mmc0clk {
				#clock-cells = <0>;
				compatible = "arkmiro,ark-clk-sys";
				clocks = <&xtal24mhz>,<&ahbpll>;
				reg = <0x50>;
				index-offset = <7>;
				index-mask = <0x1>;
				index-value = <1>;
				div-offset = <0>;
				div-mask = <0x1f>;
				div-value = <6>;
				div-mode = <ARK_CLK_DIVMODE_PONEDOUBLE>;
			};

			mmc1clk: mmc1clk {
				#clock-cells = <0>;
				compatible = "arkmiro,ark-clk-sys";
				clocks = <&xtal24mhz>,<&ahbpll>;
				reg = <0x94>;
				index-offset = <7>;
				index-mask = <0x1>;
				index-value = <1>;
				div-offset = <0>;
				div-mask = <0x1f>;
				div-value = <6>;
				div-mode = <ARK_CLK_DIVMODE_PONEDOUBLE>;
				enable-reg = <0x94>;
				enable-offset = <6>;
				//status = "disabled";
			};


			lcdclkdiv: lcdclkdiv {
				#clock-cells = <0>;
				compatible = "arkmiro,ark-clk-sys";
				clocks = <&vpupll>, <&syspll>, <&tvpll>, <&xtal24mhz>;
				reg = <0xcc>;
				index-offset = <7>;
				index-mask = <0x7>;
				index-value = <1>;
				div-offset = <4>;
				div-mask = <0x7>;
				div-value = <1>;
				div-mode = <ARK_CLK_DIVMODE_PLUSONE>;
			};

			lcdclk: lcdclk {
				#clock-cells = <0>;
				compatible = "arkmiro,ark-clk-sys";
				clocks = <&lcdclkdiv>;
				reg = <0xcc>;
				div-offset = <19>;
				div-mask = <0xf>;
				div-value = <3>;
				div-mode = <ARK_CLK_DIVMODE_PLUSONE>;
				clk-can-change;
				enable-reg = <0x54 0x54 0x3c>;
				enable-offset = <17 0 1>;

			};

			lcdscalclk: lcdscalclk {
				#clock-cells = <0>;
				compatible = "arkmiro,ark-clk-sys";
				clocks = <&lcdclkdiv>;
				reg = <0xcc>;
				div-offset = <0>;
				div-mask = <0xf>;
				div-value = <2>;
				div-mode = <ARK_CLK_DIVMODE_PLUSONE>;
			};

			mfcclk: mfcclk {
				#clock-cells = <0>;
				compatible = "arkmiro,ark-clk-sys";
				clocks = <&syspll>,<&mfcpll>, <&xtal24mhz>;
				reg = <0x78>;
				index-offset = <8>;
				index-mask = <0x3>;
				index-value = <0>;
				div-offset = <11>;
				div-mask = <0x1f>;
				div-value = <2>;
				div-mode = <ARK_CLK_DIVMODE_PLUSONE>;
			};

			vgclk: vgclk {
				#clock-cells = <0>;
				compatible = "arkmiro,ark-clk-sys";
				clocks = <&syspll>, <&gpupll>, <&xtal24mhz>;
				reg = <0xA8>;
				index-offset = <0>;
				index-mask = <0x3>;
				index-value = <1>;
				div-offset = <3>;
				div-mask = <0x1f>;
				div-value = <1>;
				div-mode = <ARK_CLK_DIVMODE_PLUSONE>;
				enable-reg = <0x54 0x54 0x64>;
				enable-offset = <12 8 13>;
			};

			gpuclk: gpuclk {
				#clock-cells = <0>;
				compatible = "arkmiro,ark-clk-sys";
				clocks = <&syspll>, <&gpupll>, <&xtal24mhz>;
				reg = <0xAC>;
				index-offset = <0>;
				index-mask = <0x3>;
				index-value = <1>;
				div-offset = <3>;
				div-mask = <0x1f>;
				div-value = <1>;
				div-mode = <ARK_CLK_DIVMODE_PLUSONE>;
				enable-reg = <0x54 0x54 0x60>;
				enable-offset = <19 5 23>;
			};


			scalclk: scalclk {
				#clock-cells = <0>;
				compatible = "arkmiro,ark-clk-sys";
				clocks = <&vpupll>, <&syspll>, <&tvpll>, <&xtal24mhz>;
				reg = <0xD8>;
				index-offset = <12>;
				index-mask = <0x7>;
				index-value = <1>;
				div-offset = <8>;
				div-mask = <0xf>;
				div-value = <2>;
				div-mode = <ARK_CLK_DIVMODE_PLUSONE>;
			};

			mac_txclk: mac_txclk {
				#clock-cells = <0>;
				compatible = "arkmiro,ark-clk-sys";
				clocks = <&cpupll>,<&xtal24mhz>;
				reg = <0x234>;
				index-offset = <29>;
				index-mask = <0x7>;
				index-value = <2>;
				div-offset = <24>;
				div-mask = <0xf>;
				div-value = <8>;
				div-mode = <ARK_CLK_DIVMODE_PLUSONE>;
				enable-reg = <0x234>;
				enable-offset = <28>;
				clk-can-change;
				status = "disabled";
			};


			i2s0_adac_clk: i2s0_adac_clk {
				#clock-cells = <0>;
				compatible = "arkmiro,ark-clk-sys";
				clocks = <&syspll>, <&cpupll>,<&xtal24mhz>;
				reg = <0x4c>;
				index-offset = <0>;
				index-mask = <0x1>;
				index-value = <0>;
			};

			i2s1_adac_clk: i2s1_adac_clk {
				#clock-cells = <0>;
				compatible = "arkmiro,ark-clk-sys";
				clocks = <&syspll>, <&cpupll>,<&xtal24mhz>;
				reg = <0x4c>;
				index-offset = <8>;
				index-mask = <0x1>;
				index-value = <0>;
			};

			i2s2_adac_clk: i2s2_adac_clk {
				#clock-cells = <0>;
				compatible = "arkmiro,ark-clk-sys";
				clocks = <&syspll>, <&cpupll>,<&xtal24mhz>;
				reg = <0x4c>;
				index-offset = <16>;
				index-mask = <0x1>;
				index-value = <0>;
			};

		};
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		gic: interrupt-controller@e0b01000 {
			compatible = "arm,cortex-a7-gic";
			interrupt-controller;
			#interrupt-cells = <3>;
			reg = <0xe0b01000 0x1000>,
			      <0xe0b02000 0x2000>,
			      <0xe0b04000 0x2000>,
			      <0xe0b06000 0x2000>;
			//interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
		};

		pinctrl0: pinctrl@50000000 {
			compatible = "arkmicro,arke-pinctrl";/**"arkmicro,ark1668ed-pinctrl";**/
			reg = <0x50000000 0x1000>;
			pad-reg-offset = <0x140>;
			npins = <192>;//189
			gpio-mux-pins = <189>;
		};
#if 1
		dmac: dmac@40200000 {
			compatible = "arkmicro,ark-dma";
			reg = <0x40200000 0x1000>;
			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
			dma-channels = <8>;
			dma-masters = <2>;
			chan_allocation_order = <1>;
			chan_priority = <1>;

			block_size = <0xfff>;
			data-width = <4 4>;
			/* multi-block = <1 1 1 1 1 1 1 1>; */
			clocks = <&clk24mhz>;
			clock-names = "hclk";
			#dma-cells = <3>;
		};
#else
		dmac: dmac@40200000 {
		  compatible = "snps,dma-spear1340";
		  reg = <0x40200000 0x1000>;
		  interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;


		  dma-channels = <8>;
		  dma-requests = <32>;
		  dma-masters = <2>;
		  #dma-cells = <3>;
		  dma-cap-mask = <0x600>;
		  chan_allocation_order = <1>;
		  chan_priority = <1>;
		  block_size = <0xfff>;
		  data-width = <4 4>;
		  multi-block = <0 0 0 0 0 0 0 0>;
		  snps,max-burst-len = <16 16 4 4 4 4 4 4>;
		};
#endif

		i2s0_adac: i2s0-adac@50d00000 {
			compatible = "arkmicro,ark1668ed-i2s";
			reg = <0x50d00000 0x1000
					0x50000000 0x1000>;
			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
			adc-nco-reg = <0x50000080>;
			nco-reg = <0x5000007c>;
			//full-duplex-mode;
			index = <0>;
			dmas = <&dmac 16 1 0>, <&dmac 17 1 0>;
			dma-names = "rx", "tx";
			clocks = <&i2s0_adac_clk>;
			pinctrl-0 = <&pinctrl_i2s0dac_sadata_out0 &pinctrl_i2s0dac_sadata_out1 &pinctrl_i2s0dac_sadata_out2
							 &pinctrl_i2s0dac_sync &pinctrl_i2s0dac_mclk &pinctrl_i2s0dac_bclk
							&pinctrl_i2s0adc_sadata_in0 &pinctrl_i2s0adc_sadata_in1
							&pinctrl_i2s0adc_sync &pinctrl_i2s0adc_mclk &pinctrl_i2s0adc_bclk>;
			pinctrl-names = "default";
			#sound-dai-cells = <0>;
		};

		i2s1_adac: i2s1-adac@50e00000 {
			compatible = "arkmicro,ark1668ed-i2s";
			reg = <0x50e00000 0x1000
					0x50000000 0x1000>;
			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
			adc-nco-reg = <0x50000088>;
			nco-reg = <0x50000084>;
			//full-duplex-mode;
			index = <1>;
			dmas = <&dmac 18 1 0>, <&dmac 19 1 0>;
			dma-names = "rx", "tx";
			clocks = <&i2s1_adac_clk>;
			pinctrl-0 = <&pinctrl_i2s1dac_sadata_out0 &pinctrl_i2s1dac_sadata_out1 &pinctrl_i2s1dac_sadata_out2
							&pinctrl_i2s1dac_sync &pinctrl_i2s1dac_mclk &pinctrl_i2s1dac_bclk
							&pinctrl_i2s1adc_sadata_in0 &pinctrl_i2s1adc_sadata_in1
							&pinctrl_i2s1adc_sync &pinctrl_i2s1adc_mclk &pinctrl_i2s1adc_bclk>;
			pinctrl-names = "default";
			#sound-dai-cells = <0>;
		};

		i2s_audio: i2s-audio@50100000 {
			compatible = "arkmicro,ark1668ed-i2s";
			reg = <0x50100000 0x1000
					0x50000000 0x1000>;
			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
			adc-nco-reg = <0x50000090>;
			nco-reg = <0x5000008c>;
			full-duplex-mode;
			index = <2>;
			dmas = <&dmac 20 1 0>, <&dmac 21 1 0>;
			dma-names = "rx", "tx";
			clocks = <&i2s2_adac_clk>;
			#sound-dai-cells = <0>;
		};

		uart0: uart@50500000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x50500000 0x1000>;
			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk24mhz>;
			reg-shift = <2>;
//			pinctrl-names = "default";
//			pinctrl-0 = <&pinctrl_uart0>;
			//dmas = <&dmac 6 1 0>, <&dmac 7 0 1>;
			//dma-names = "rx", "tx";
		};

		uart1: uart@50600000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x50600000 0x1000>;
			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
			current-speed = <115200>;
			clocks = <&clk24mhz>;
			reg-shift = <2>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart1>;
			//dmas = <&dmac 12 1 0>, <&dmac 13 0 1>;
			//dma-names = "rx", "tx";
			status = "okay";
		};

		uart2: uart@50700000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x50700000 0x1000>;
			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
			current-speed = <115200>;
			clocks = <&clk24mhz>;
			reg-shift = <2>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart2>;
			//dmas = <&dmac 19 1 0>, <&dmac 20 0 1>;
			//dma-names = "rx", "tx";
			status = "okay";
		};

		uart3: uart@50800000 {
			//compatible = "arkmicro,ark-uart";
			compatible = "snps,dw-apb-uart";
			reg = <0x50800000 0x1000>;
			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
			current-speed = <115200>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart3>;
			clocks = <&clk24mhz>;
			reg-shift = <2>;
			//dmas = <&dmac 21 1 0>, <&dmac 22 0 1>;
			//dma-names = "rx", "tx";
			status = "disabled";
		};

		uart4: uart@51300000 {
			//compatible = "arkmicro,ark-uart";
			compatible = "snps,dw-apb-uart";
			reg = <0x51300000 0x4000>;
			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk24mhz>;
			reg-shift = <2>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart4>;
			//dmas = <&dmac 14 1 0>, <&dmac 15 0 1>;
			//dma-names = "rx", "tx";
			status = "disabled";
		};

		uart5: uart@51d00000 {
			//compatible = "arkmicro,ark-uart";
			compatible = "snps,dw-apb-uart";
			reg = <0x51d00000 0x4000>;
			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk24mhz>;
			reg-shift = <2>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart5>;
			//dmas = <&dmac 16 1 0>, <&dmac 17 0 1>;
			//dma-names = "rx", "tx";
			status = "okay";
		};

		timer: timer@50a00000 {
			compatible = "snps,dw-apb-timer-osc";
			reg = <0x50a00000 0x1000>;
			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk12mhz>, <&clk24mhz>;
			clock-names = "timer", "pclk";
			status = "disabled";
		};

		watchdog: watchdog@50c00000 {
			compatible = "arkmicro,ark-wdt";
			reg = <0x50c00000 0x20>;
			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&pclk>;

		};

		gpio0: gpio@50900000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,dw-apb-gpio";
			reg = <0x50900000 0x80>;

			gporta: gpio-port@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				snps,nr-gpios = <32>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
				gpio-ranges = <&pinctrl0 0 0 32>;
			};
		};

		gpio1: gpio@50900080 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,dw-apb-gpio";
			reg = <0x50900080 0x80>;

			gportb: gpio-port@1 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				snps,nr-gpios = <32>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
				gpio-ranges = <&pinctrl0 0 32 32>;
			};
		};

		gpio2: gpio@50900100 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,dw-apb-gpio";
			reg = <0x50900100 0x80>;
//			status = "disabled";
			gportc: gpio-port@2 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				snps,nr-gpios = <32>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
				gpio-ranges = <&pinctrl0 0 64 32>;
			};
		};

		gpio3: gpio@50900180 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,dw-apb-gpio";
			reg = <0x50900180 0x80>;
//			status = "disabled";
			gportd: gpio-port@3 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				snps,nr-gpios = <32>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
				gpio-ranges = <&pinctrl0 0 96 32>;
			};
		};

		gpio4: gpio@50900200 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,dw-apb-gpio";
			reg = <0x50900200 0x80>;
			gporte: gpio-port@4 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				snps,nr-gpios = <32>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
				gpio-ranges = <&pinctrl0 0 128 32>;
			};
		};

		gpio5: gpio@50900280 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,dw-apb-gpio";
			reg = <0x50900280 0x80>;
			gportf: gpio-port@5 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				snps,nr-gpios = <32>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
				gpio-ranges = <&pinctrl0 0 160 32>;
			};
		};

		nfc: nand@20000000 {
			compatible = "arkmicro,ark-nand";
			reg = <0x20000000 0x1000>;
			max-chips = <1>;
			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
			nand-bus-width = <8>;
			//nand-ecc-mode = "hw_syndrome";
			nand-ecc-mode = "hw";
			nand-ecc-placement = "oob";
			nand-on-flash-bbt;
		};


		pwm0: pwm@50b00000 {
			compatible = "arkmicro,ark-pwm";
			reg = <0x50b00000 0x1000>;
			#pwm-cells = <3>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_pwm0 &pinctrl_pwm3 &pinctrl_pwm4>;
			clocks = <&clk24mhz>;
		};

		mmc0: mmc@40100000 {
			compatible = "snps,dw-mshc";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40100000 0x1000>;
			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
			fifo-depth = <64>;
			bus-width = <8>;
			cap-mmc-highspeed;
			disable-wp;
			non-removable;
			clocks = <&mmc0clk>;
			//clock-frequency= <24000000>;
			clock-names = "ciu";
		};

		mmc1: mmc@40400000 {
			compatible = "snps,dw-mshc";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40400000 0x1000>;
			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
			fifo-depth = <64>;
			bus-width = <8>;
			//non-removable;
			//cap-power-off-card;
			//keep-power-in-suspend;
			//supports-SDIO;
			cap-sd-highspeed;
			cap-sdio-irq;
			//broken-cd;
			clocks = <&mmc1clk>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_mmc1>;
			clock-names = "ciu";
		};

		i2c0: i2c@50300000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0x50300000 0x1000>;
			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c0>;
			clocks = <&clk24mhz>;
			clock-frequency = <400000>;
		};

		i2c1: i2c@50400000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0x50400000 0x1000>;
			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
//			pinctrl-0 = <&pinctrl_i2c1>;
			clocks = <&clk12mhz>;
			status = "disabled";

		};

#if 0
		dwssi: dwssi@30000000 {
			//compatible = "arkmicro,ark-dw-ssi";
			//compatible = "snps,dw-apb-ssi";
			compatible = "snps,dwc-ssi-1.01a";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x30000000 0x100>;
			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
			num-cs = <1>;
			//cs-gpios = <&gportd 14 0>;

			//dmas = <&dmac 0 1 0>, <&dmac 1 0 1>;
			//dma-names = "rx", "tx";

			//pinctrl-names = "default";
			//pinctrl-0 = <&pinctrl_dwssi_0>;
			clocks = <&clk24mhz>;
			//reg-io-width = <1>;
			status = "disabled";

			m25p80@0 {
				#address-cells = <1>;
				#size-cells = <1>;
				compatible = "w25q256";
				reg = <0>; /* Chip select 0 */
				spi-max-frequency = <3000000>;
				//spi-tx-bus-width = <1>;
				//spi-rx-bus-width = <4>;
				//status = "disabled";
			};

			gd5f@0 {
				#address-cells = <1>;
				#size-cells = <1>;
				compatible = "gd5f";
				reg = <0>; /* Chip select 0 */
				spi-max-frequency = <3000000>;
				status = "disabled";
			};
		};
#endif
		gpu0: gpu@40600000 {
			compatible = "arkmicro,ark1668ed_gc555";
			reg = <0x40600000 0x1000>;
			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
		};


		vdec0: vdec@40700000 {
			compatible = "on2,ark-vdec";
			reg = <0x40700000 0x1000
					0x7c000000 0x500000>;

			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&mfcclk>;
			clock-names = "vdec_clk";
			//status = "disabled";
		};

		axi_scale: axi-scale@41000000 {
			compatible = "arkmicro,ark1668ed-axi-scale";
			reg = <0x41000000 0x1000
					0x50000000 0x1000>;
			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&scalclk>;
			clock-names = "scale_clk";
			//softreset-reg = <0x74>;
			//softreset-offset = <28>;
		};

		gpu_2d: gpu-2d@40500000 {
			compatible = "arkmicro,gpu-2d";
			reg = <0x40500000 0x1000>;
			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
			contiguousSize = <0x1000000>;
			powerManagement = <0>;
		};

		ethernet: ethernet@40b00000 {
			compatible = "snps,dwc-qos-ethernet-4.10";
			reg = <0x40b00000 0x4000>;
			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
			snps,write-requests = <2>;
			snps,read-requests = <16>;
			snps,txpbl = <8>;
			snps,rxpbl = <2>;
//			snps,reset-gpio = <&gportd 15 GPIO_ACTIVE_LOW>;
			snps,reset-active-low;
			snps,reset-delays-us = <0 10000 1000000>;
//			clocks = <&eth_phy_ref_clk>, <&eth_phy_ref_clk>;
			clock-names = "phy_ref_clk", "apb_pclk";
//			status = "disabled";
		};

		lcdc: lcd@40300000 {
			compatible = "arkmicro,ark1668e-lcdc";
			reg = <0x40300000 0x1000
					0x7d000000 0x3000000
					0x51b00000 0x100>;
			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&lcdclk>, <&lcdscalclk>;
			clock-names = "lcdc_clk", "lcd_scalclk";
		};

		usb0_phy: usb0-phy {
			compatible = "usb-nop-xceiv";
			#phy-cells = <0>;
			status = "OK";
		};

		usb1_phy: usb1-phy {
			compatible = "usb-nop-xceiv";
			#phy-cells = <0>;
			status = "OK";
		};

		usb0: usb@40000000 {
			compatible = "snps,dwc2";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40000000 0x40000 /* usb base address */
					0x50000000 0x1000>;/* sys base address */
			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
			phys = <&usb0_phy>;
			phy-names = "usb0-phy";
			//dr_mode = "host";
			usb-role-switch;
			role-switch-default-mode = "host";
			dr_mode = "otg";
			usb-id-reg = <0x100>;
			usb-id-bit-offset = <16>;
		};

		usb1: usb@40c00000 {
			compatible = "snps,dwc2";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40c00000 0x40000 /* usb base address */
					0x50000000 0x1000>;/* sys base address */
			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
			phys = <&usb1_phy>;
			phy-names = "usb1-phy";
			//dr_mode = "host";
			usb-role-switch;
			role-switch-default-mode = "host";
			dr_mode = "otg";
			usb-id-reg = <0x100>;
			usb-id-bit-offset = <24>;
		};
	};
};