serval_pcb105.dts 1.6 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * Copyright (c) 2018 Microsemi Corporation
  4. */
  5. /dts-v1/;
  6. #include "mscc,serval.dtsi"
  7. #include <dt-bindings/mscc/serval_data.h>
  8. / {
  9. model = "Serval PCB105 Reference Board";
  10. compatible = "mscc,serval-pcb105", "mscc,serval";
  11. aliases {
  12. spi0 = &spi0;
  13. serial0 = &uart0;
  14. };
  15. chosen {
  16. stdout-path = "serial0:115200n8";
  17. };
  18. gpio-leds {
  19. compatible = "gpio-leds";
  20. status_green {
  21. label = "pcb105:green:status";
  22. gpios = <&sgpio 43 1>; /* p11.1 */
  23. default-state = "on";
  24. };
  25. status_red {
  26. label = "pcb105:red:status";
  27. gpios = <&sgpio 11 1>; /* p11.0 */
  28. default-state = "off";
  29. };
  30. };
  31. };
  32. &uart0 {
  33. status = "okay";
  34. };
  35. &spi0 {
  36. status = "okay";
  37. spi-flash@0 {
  38. compatible = "jedec,spi-nor";
  39. spi-max-frequency = <18000000>; /* input clock */
  40. reg = <0>; /* CS0 */
  41. spi-cs-high;
  42. };
  43. };
  44. &sgpio {
  45. status = "okay";
  46. sgpio-ports = <0x00FFFFFF>;
  47. };
  48. &mdio1 {
  49. status = "okay";
  50. phy16: ethernet-phy@16 {
  51. reg = <16>;
  52. };
  53. phy17: ethernet-phy@17 {
  54. reg = <17>;
  55. };
  56. phy18: ethernet-phy@18 {
  57. reg = <18>;
  58. };
  59. phy19: ethernet-phy@19 {
  60. reg = <19>;
  61. };
  62. };
  63. &switch {
  64. ethernet-ports {
  65. port0: port@0 {
  66. reg = <7>;
  67. phy-handle = <&phy16>;
  68. phys = <&serdes_hsio 7 SERDES1G(7) PHY_MODE_SGMII>;
  69. };
  70. port1: port@1 {
  71. reg = <6>;
  72. phy-handle = <&phy17>;
  73. phys = <&serdes_hsio 6 SERDES1G(6) PHY_MODE_SGMII>;
  74. };
  75. port2: port@2 {
  76. reg = <5>;
  77. phy-handle = <&phy18>;
  78. phys = <&serdes_hsio 5 SERDES1G(5) PHY_MODE_SGMII>;
  79. };
  80. port3: port@3 {
  81. reg = <4>;
  82. phy-handle = <&phy19>;
  83. phys = <&serdes_hsio 4 SERDES1G(4) PHY_MODE_SGMII>;
  84. };
  85. };
  86. };