rockchip,dwc-ahci.yaml 2.8 KB

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  1. # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2. %YAML 1.2
  3. ---
  4. $id: http://devicetree.org/schemas/ata/rockchip,dwc-ahci.yaml#
  5. $schema: http://devicetree.org/meta-schemas/core.yaml#
  6. title: Synopsys DWC AHCI SATA controller for Rockchip devices
  7. maintainers:
  8. - Serge Semin <fancer.lancer@gmail.com>
  9. description:
  10. This document defines device tree bindings for the Synopsys DWC
  11. implementation of the AHCI SATA controller found in Rockchip
  12. devices.
  13. select:
  14. properties:
  15. compatible:
  16. contains:
  17. enum:
  18. - rockchip,rk3568-dwc-ahci
  19. - rockchip,rk3588-dwc-ahci
  20. required:
  21. - compatible
  22. properties:
  23. compatible:
  24. items:
  25. - enum:
  26. - rockchip,rk3568-dwc-ahci
  27. - rockchip,rk3588-dwc-ahci
  28. - const: snps,dwc-ahci
  29. ports-implemented:
  30. const: 1
  31. power-domains:
  32. maxItems: 1
  33. sata-port@0:
  34. $ref: /schemas/ata/snps,dwc-ahci-common.yaml#/$defs/dwc-ahci-port
  35. properties:
  36. reg:
  37. const: 0
  38. unevaluatedProperties: false
  39. patternProperties:
  40. "^sata-port@[1-9a-e]$": false
  41. required:
  42. - compatible
  43. - reg
  44. - interrupts
  45. - clocks
  46. - clock-names
  47. - ports-implemented
  48. allOf:
  49. - $ref: snps,dwc-ahci-common.yaml#
  50. - if:
  51. properties:
  52. compatible:
  53. contains:
  54. enum:
  55. - rockchip,rk3588-dwc-ahci
  56. then:
  57. properties:
  58. clocks:
  59. maxItems: 5
  60. clock-names:
  61. items:
  62. - const: sata
  63. - const: pmalive
  64. - const: rxoob
  65. - const: ref
  66. - const: asic
  67. - if:
  68. properties:
  69. compatible:
  70. contains:
  71. enum:
  72. - rockchip,rk3568-dwc-ahci
  73. then:
  74. properties:
  75. clocks:
  76. maxItems: 3
  77. clock-names:
  78. items:
  79. - const: sata
  80. - const: pmalive
  81. - const: rxoob
  82. unevaluatedProperties: false
  83. examples:
  84. - |
  85. #include <dt-bindings/clock/rockchip,rk3588-cru.h>
  86. #include <dt-bindings/interrupt-controller/arm-gic.h>
  87. #include <dt-bindings/ata/ahci.h>
  88. #include <dt-bindings/phy/phy.h>
  89. sata@fe210000 {
  90. compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
  91. reg = <0xfe210000 0x1000>;
  92. clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>,
  93. <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>,
  94. <&cru CLK_PIPEPHY0_PIPE_ASIC_G>;
  95. clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
  96. interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH 0>;
  97. ports-implemented = <0x1>;
  98. #address-cells = <1>;
  99. #size-cells = <0>;
  100. sata-port@0 {
  101. reg = <0>;
  102. hba-port-cap = <HBA_PORT_FBSCP>;
  103. phys = <&combphy0_ps PHY_TYPE_SATA>;
  104. phy-names = "sata-phy";
  105. snps,rx-ts-max = <32>;
  106. snps,tx-ts-max = <32>;
  107. };
  108. };
  109. ...