baikal,bt1-axi.yaml 2.5 KB

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  1. # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2. # Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
  3. %YAML 1.2
  4. ---
  5. $id: http://devicetree.org/schemas/bus/baikal,bt1-axi.yaml#
  6. $schema: http://devicetree.org/meta-schemas/core.yaml#
  7. title: Baikal-T1 AXI-bus
  8. maintainers:
  9. - Serge Semin <fancer.lancer@gmail.com>
  10. description: |
  11. AXI3-bus is the main communication bus of Baikal-T1 SoC connecting all
  12. high-speed peripheral IP-cores with RAM controller and with MIPS P5600
  13. cores. Traffic arbitration is done by means of DW AXI Interconnect (so
  14. called AXI Main Interconnect) routing IO requests from one block to
  15. another: from CPU to SoC peripherals and between some SoC peripherals
  16. (mostly between peripheral devices and RAM, but also between DMA and
  17. some peripherals). In case of any protocol error, device not responding
  18. an IRQ is raised and a faulty situation is reported to the AXI EHB
  19. (Errors Handler Block) embedded on top of the DW AXI Interconnect and
  20. accessible by means of the Baikal-T1 System Controller.
  21. allOf:
  22. - $ref: /schemas/simple-bus.yaml#
  23. properties:
  24. compatible:
  25. contains:
  26. const: baikal,bt1-axi
  27. reg:
  28. minItems: 1
  29. items:
  30. - description: Synopsys DesignWare AXI Interconnect QoS registers
  31. - description: AXI EHB MMIO system controller registers
  32. reg-names:
  33. minItems: 1
  34. items:
  35. - const: qos
  36. - const: ehb
  37. '#interconnect-cells':
  38. const: 1
  39. syscon:
  40. $ref: /schemas/types.yaml#/definitions/phandle
  41. description: Phandle to the Baikal-T1 System Controller DT node
  42. interrupts:
  43. maxItems: 1
  44. clocks:
  45. items:
  46. - description: Main Interconnect uplink reference clock
  47. clock-names:
  48. items:
  49. - const: aclk
  50. resets:
  51. items:
  52. - description: Main Interconnect reset line
  53. reset-names:
  54. items:
  55. - const: arst
  56. unevaluatedProperties: false
  57. required:
  58. - compatible
  59. - reg
  60. - reg-names
  61. - syscon
  62. - interrupts
  63. - clocks
  64. - clock-names
  65. examples:
  66. - |
  67. #include <dt-bindings/interrupt-controller/mips-gic.h>
  68. bus@1f05a000 {
  69. compatible = "baikal,bt1-axi", "simple-bus";
  70. reg = <0x1f05a000 0x1000>,
  71. <0x1f04d110 0x8>;
  72. reg-names = "qos", "ehb";
  73. #address-cells = <1>;
  74. #size-cells = <1>;
  75. #interconnect-cells = <1>;
  76. syscon = <&syscon>;
  77. ranges;
  78. interrupts = <GIC_SHARED 127 IRQ_TYPE_LEVEL_HIGH>;
  79. clocks = <&ccu_axi 0>;
  80. clock-names = "aclk";
  81. resets = <&ccu_axi 0>;
  82. reset-names = "arst";
  83. };
  84. ...