nvidia,tegra30-actmon.yaml 2.9 KB

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  1. # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2. %YAML 1.2
  3. ---
  4. $id: http://devicetree.org/schemas/devfreq/nvidia,tegra30-actmon.yaml#
  5. $schema: http://devicetree.org/meta-schemas/core.yaml#
  6. title: NVIDIA Tegra30 Activity Monitor
  7. maintainers:
  8. - Dmitry Osipenko <digetx@gmail.com>
  9. - Jon Hunter <jonathanh@nvidia.com>
  10. - Thierry Reding <thierry.reding@gmail.com>
  11. description: |
  12. The activity monitor block collects statistics about the behaviour of other
  13. components in the system. This information can be used to derive the rate at
  14. which the external memory needs to be clocked in order to serve all requests
  15. from the monitored clients.
  16. properties:
  17. compatible:
  18. enum:
  19. - nvidia,tegra30-actmon
  20. - nvidia,tegra114-actmon
  21. - nvidia,tegra124-actmon
  22. - nvidia,tegra210-actmon
  23. reg:
  24. maxItems: 1
  25. clocks:
  26. maxItems: 2
  27. clock-names:
  28. items:
  29. - const: actmon
  30. - const: emc
  31. resets:
  32. maxItems: 1
  33. reset-names:
  34. items:
  35. - const: actmon
  36. interrupts:
  37. maxItems: 1
  38. interconnects:
  39. minItems: 1
  40. maxItems: 12
  41. interconnect-names:
  42. minItems: 1
  43. maxItems: 12
  44. description:
  45. Should include name of the interconnect path for each interconnect
  46. entry. Consult TRM documentation for information about available
  47. memory clients, see MEMORY CONTROLLER and ACTIVITY MONITOR sections.
  48. operating-points-v2:
  49. description:
  50. Should contain freqs and voltages and opp-supported-hw property, which
  51. is a bitfield indicating SoC speedo ID mask.
  52. "#cooling-cells":
  53. const: 2
  54. required:
  55. - compatible
  56. - reg
  57. - clocks
  58. - clock-names
  59. - resets
  60. - reset-names
  61. - interrupts
  62. - interconnects
  63. - interconnect-names
  64. - operating-points-v2
  65. - "#cooling-cells"
  66. additionalProperties: false
  67. examples:
  68. - |
  69. #include <dt-bindings/memory/tegra30-mc.h>
  70. mc: memory-controller@7000f000 {
  71. compatible = "nvidia,tegra30-mc";
  72. reg = <0x7000f000 0x400>;
  73. clocks = <&clk 32>;
  74. clock-names = "mc";
  75. interrupts = <0 77 4>;
  76. #iommu-cells = <1>;
  77. #reset-cells = <1>;
  78. #interconnect-cells = <1>;
  79. };
  80. emc: external-memory-controller@7000f400 {
  81. compatible = "nvidia,tegra30-emc";
  82. reg = <0x7000f400 0x400>;
  83. interrupts = <0 78 4>;
  84. clocks = <&clk 57>;
  85. nvidia,memory-controller = <&mc>;
  86. operating-points-v2 = <&dvfs_opp_table>;
  87. power-domains = <&domain>;
  88. #interconnect-cells = <0>;
  89. };
  90. actmon@6000c800 {
  91. compatible = "nvidia,tegra30-actmon";
  92. reg = <0x6000c800 0x400>;
  93. interrupts = <0 45 4>;
  94. clocks = <&clk 119>, <&clk 57>;
  95. clock-names = "actmon", "emc";
  96. resets = <&rst 119>;
  97. reset-names = "actmon";
  98. operating-points-v2 = <&dvfs_opp_table>;
  99. interconnects = <&mc TEGRA30_MC_MPCORER &emc>;
  100. interconnect-names = "cpu-read";
  101. #cooling-cells = <2>;
  102. };