mediatek,hdmi.yaml 3.1 KB

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  1. # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2. %YAML 1.2
  3. ---
  4. $id: http://devicetree.org/schemas/display/mediatek/mediatek,hdmi.yaml#
  5. $schema: http://devicetree.org/meta-schemas/core.yaml#
  6. title: Mediatek HDMI Encoder
  7. maintainers:
  8. - CK Hu <ck.hu@mediatek.com>
  9. - Jitao shi <jitao.shi@mediatek.com>
  10. description: |
  11. The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from
  12. its parallel input.
  13. properties:
  14. compatible:
  15. enum:
  16. - mediatek,mt2701-hdmi
  17. - mediatek,mt7623-hdmi
  18. - mediatek,mt8167-hdmi
  19. - mediatek,mt8173-hdmi
  20. reg:
  21. maxItems: 1
  22. interrupts:
  23. maxItems: 1
  24. clocks:
  25. items:
  26. - description: Pixel Clock
  27. - description: HDMI PLL
  28. - description: Bit Clock
  29. - description: S/PDIF Clock
  30. clock-names:
  31. items:
  32. - const: pixel
  33. - const: pll
  34. - const: bclk
  35. - const: spdif
  36. phys:
  37. maxItems: 1
  38. phy-names:
  39. items:
  40. - const: hdmi
  41. mediatek,syscon-hdmi:
  42. $ref: /schemas/types.yaml#/definitions/phandle-array
  43. items:
  44. - items:
  45. - description: phandle to system configuration registers
  46. - description: register offset in the system configuration registers
  47. description: |
  48. phandle link and register offset to the system configuration registers.
  49. ports:
  50. $ref: /schemas/graph.yaml#/properties/ports
  51. properties:
  52. port@0:
  53. $ref: /schemas/graph.yaml#/properties/port
  54. description: |
  55. Input port node. This port should be connected to a DPI output port.
  56. port@1:
  57. $ref: /schemas/graph.yaml#/properties/port
  58. description: |
  59. Output port node. This port should be connected to the input port of a connector
  60. node that contains a ddc-i2c-bus property, or to the input port of an attached
  61. bridge chip, such as a SlimPort transmitter.
  62. required:
  63. - port@0
  64. - port@1
  65. required:
  66. - compatible
  67. - reg
  68. - interrupts
  69. - clocks
  70. - clock-names
  71. - phys
  72. - phy-names
  73. - mediatek,syscon-hdmi
  74. - ports
  75. additionalProperties: false
  76. examples:
  77. - |
  78. #include <dt-bindings/clock/mt8173-clk.h>
  79. #include <dt-bindings/interrupt-controller/arm-gic.h>
  80. #include <dt-bindings/interrupt-controller/irq.h>
  81. hdmi0: hdmi@14025000 {
  82. compatible = "mediatek,mt8173-hdmi";
  83. reg = <0x14025000 0x400>;
  84. interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>;
  85. clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
  86. <&mmsys CLK_MM_HDMI_PLLCK>,
  87. <&mmsys CLK_MM_HDMI_AUDIO>,
  88. <&mmsys CLK_MM_HDMI_SPDIF>;
  89. clock-names = "pixel", "pll", "bclk", "spdif";
  90. pinctrl-names = "default";
  91. pinctrl-0 = <&hdmi_pin>;
  92. phys = <&hdmi_phy>;
  93. phy-names = "hdmi";
  94. mediatek,syscon-hdmi = <&mmsys 0x900>;
  95. ports {
  96. #address-cells = <1>;
  97. #size-cells = <0>;
  98. port@0 {
  99. reg = <0>;
  100. hdmi0_in: endpoint {
  101. remote-endpoint = <&dpi0_out>;
  102. };
  103. };
  104. port@1 {
  105. reg = <1>;
  106. hdmi0_out: endpoint {
  107. remote-endpoint = <&hdmi_con_in>;
  108. };
  109. };
  110. };
  111. };
  112. ...