| 123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114 |
- # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
- %YAML 1.2
- ---
- $id: http://devicetree.org/schemas/display/mediatek/mediatek,split.yaml#
- $schema: http://devicetree.org/meta-schemas/core.yaml#
- title: Mediatek display split
- maintainers:
- - Chun-Kuang Hu <chunkuang.hu@kernel.org>
- - Philipp Zabel <p.zabel@pengutronix.de>
- description: |
- Mediatek display split, namely SPLIT, is used to split stream to two
- encoders.
- SPLIT device node must be siblings to the central MMSYS_CONFIG node.
- For a description of the MMSYS_CONFIG binding, see
- Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
- for details.
- properties:
- compatible:
- oneOf:
- - enum:
- - mediatek,mt8173-disp-split
- - mediatek,mt8195-mdp3-split
- - items:
- - const: mediatek,mt6795-disp-split
- - const: mediatek,mt8173-disp-split
- reg:
- maxItems: 1
- interrupts:
- maxItems: 1
- power-domains:
- description: A phandle and PM domain specifier as defined by bindings of
- the power controller specified by phandle. See
- Documentation/devicetree/bindings/power/power-domain.yaml for details.
- maxItems: 1
- mediatek,gce-client-reg:
- description:
- The register of display function block to be set by gce. There are 4 arguments,
- such as gce node, subsys id, offset and register size. The subsys id that is
- mapping to the register of display function blocks is defined in the gce header
- include/dt-bindings/gce/<chip>-gce.h of each chips.
- $ref: /schemas/types.yaml#/definitions/phandle-array
- items:
- items:
- - description: phandle of GCE
- - description: GCE subsys id
- - description: register offset
- - description: register size
- maxItems: 1
- clocks:
- items:
- - description: SPLIT Clock
- - description: Used for interfacing with the HDMI RX signal source.
- - description: Paired with receiving HDMI RX metadata.
- minItems: 1
- required:
- - compatible
- - reg
- - power-domains
- - clocks
- allOf:
- - if:
- properties:
- compatible:
- contains:
- const: mediatek,mt8195-mdp3-split
- then:
- properties:
- clocks:
- minItems: 3
- required:
- - mediatek,gce-client-reg
- - if:
- properties:
- compatible:
- contains:
- const: mediatek,mt8173-disp-split
- then:
- properties:
- clocks:
- maxItems: 1
- additionalProperties: false
- examples:
- - |
- #include <dt-bindings/clock/mt8173-clk.h>
- #include <dt-bindings/power/mt8173-power.h>
- soc {
- #address-cells = <2>;
- #size-cells = <2>;
- split0: split@14018000 {
- compatible = "mediatek,mt8173-disp-split";
- reg = <0 0x14018000 0 0x1000>;
- power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
- };
- };
|