mediatek,split.yaml 2.9 KB

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  1. # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2. %YAML 1.2
  3. ---
  4. $id: http://devicetree.org/schemas/display/mediatek/mediatek,split.yaml#
  5. $schema: http://devicetree.org/meta-schemas/core.yaml#
  6. title: Mediatek display split
  7. maintainers:
  8. - Chun-Kuang Hu <chunkuang.hu@kernel.org>
  9. - Philipp Zabel <p.zabel@pengutronix.de>
  10. description: |
  11. Mediatek display split, namely SPLIT, is used to split stream to two
  12. encoders.
  13. SPLIT device node must be siblings to the central MMSYS_CONFIG node.
  14. For a description of the MMSYS_CONFIG binding, see
  15. Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
  16. for details.
  17. properties:
  18. compatible:
  19. oneOf:
  20. - enum:
  21. - mediatek,mt8173-disp-split
  22. - mediatek,mt8195-mdp3-split
  23. - items:
  24. - const: mediatek,mt6795-disp-split
  25. - const: mediatek,mt8173-disp-split
  26. reg:
  27. maxItems: 1
  28. interrupts:
  29. maxItems: 1
  30. power-domains:
  31. description: A phandle and PM domain specifier as defined by bindings of
  32. the power controller specified by phandle. See
  33. Documentation/devicetree/bindings/power/power-domain.yaml for details.
  34. maxItems: 1
  35. mediatek,gce-client-reg:
  36. description:
  37. The register of display function block to be set by gce. There are 4 arguments,
  38. such as gce node, subsys id, offset and register size. The subsys id that is
  39. mapping to the register of display function blocks is defined in the gce header
  40. include/dt-bindings/gce/<chip>-gce.h of each chips.
  41. $ref: /schemas/types.yaml#/definitions/phandle-array
  42. items:
  43. items:
  44. - description: phandle of GCE
  45. - description: GCE subsys id
  46. - description: register offset
  47. - description: register size
  48. maxItems: 1
  49. clocks:
  50. items:
  51. - description: SPLIT Clock
  52. - description: Used for interfacing with the HDMI RX signal source.
  53. - description: Paired with receiving HDMI RX metadata.
  54. minItems: 1
  55. required:
  56. - compatible
  57. - reg
  58. - power-domains
  59. - clocks
  60. allOf:
  61. - if:
  62. properties:
  63. compatible:
  64. contains:
  65. const: mediatek,mt8195-mdp3-split
  66. then:
  67. properties:
  68. clocks:
  69. minItems: 3
  70. required:
  71. - mediatek,gce-client-reg
  72. - if:
  73. properties:
  74. compatible:
  75. contains:
  76. const: mediatek,mt8173-disp-split
  77. then:
  78. properties:
  79. clocks:
  80. maxItems: 1
  81. additionalProperties: false
  82. examples:
  83. - |
  84. #include <dt-bindings/clock/mt8173-clk.h>
  85. #include <dt-bindings/power/mt8173-power.h>
  86. soc {
  87. #address-cells = <2>;
  88. #size-cells = <2>;
  89. split0: split@14018000 {
  90. compatible = "mediatek,mt8173-disp-split";
  91. reg = <0 0x14018000 0 0x1000>;
  92. power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
  93. clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
  94. };
  95. };