dp-controller.yaml 5.6 KB

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  1. # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2. %YAML 1.2
  3. ---
  4. $id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
  5. $schema: http://devicetree.org/meta-schemas/core.yaml#
  6. title: MSM Display Port Controller
  7. maintainers:
  8. - Kuogee Hsieh <quic_khsieh@quicinc.com>
  9. description: |
  10. Device tree bindings for DisplayPort host controller for MSM targets
  11. that are compatible with VESA DisplayPort interface specification.
  12. properties:
  13. compatible:
  14. oneOf:
  15. - enum:
  16. - qcom,sc7180-dp
  17. - qcom,sc7280-dp
  18. - qcom,sc7280-edp
  19. - qcom,sc8180x-dp
  20. - qcom,sc8180x-edp
  21. - qcom,sc8280xp-dp
  22. - qcom,sc8280xp-edp
  23. - qcom,sdm845-dp
  24. - qcom,sm8350-dp
  25. - qcom,sm8650-dp
  26. - items:
  27. - enum:
  28. - qcom,sm6350-dp
  29. - qcom,sm8150-dp
  30. - qcom,sm8250-dp
  31. - qcom,sm8450-dp
  32. - qcom,sm8550-dp
  33. - const: qcom,sm8350-dp
  34. reg:
  35. minItems: 4
  36. items:
  37. - description: ahb register block
  38. - description: aux register block
  39. - description: link register block
  40. - description: p0 register block
  41. - description: p1 register block
  42. interrupts:
  43. maxItems: 1
  44. clocks:
  45. items:
  46. - description: AHB clock to enable register access
  47. - description: Display Port AUX clock
  48. - description: Display Port Link clock
  49. - description: Link interface clock between DP and PHY
  50. - description: Display Port Pixel clock
  51. clock-names:
  52. items:
  53. - const: core_iface
  54. - const: core_aux
  55. - const: ctrl_link
  56. - const: ctrl_link_iface
  57. - const: stream_pixel
  58. assigned-clocks:
  59. items:
  60. - description: link clock source
  61. - description: pixel clock source
  62. assigned-clock-parents:
  63. items:
  64. - description: phy 0 parent
  65. - description: phy 1 parent
  66. phys:
  67. maxItems: 1
  68. phy-names:
  69. items:
  70. - const: dp
  71. operating-points-v2: true
  72. opp-table:
  73. type: object
  74. power-domains:
  75. maxItems: 1
  76. aux-bus:
  77. $ref: /schemas/display/dp-aux-bus.yaml#
  78. data-lanes:
  79. $ref: /schemas/types.yaml#/definitions/uint32-array
  80. deprecated: true
  81. minItems: 1
  82. maxItems: 4
  83. items:
  84. maximum: 3
  85. "#sound-dai-cells":
  86. const: 0
  87. vdda-0p9-supply:
  88. deprecated: true
  89. vdda-1p2-supply:
  90. deprecated: true
  91. ports:
  92. $ref: /schemas/graph.yaml#/properties/ports
  93. properties:
  94. port@0:
  95. $ref: /schemas/graph.yaml#/properties/port
  96. description: Input endpoint of the controller
  97. port@1:
  98. $ref: /schemas/graph.yaml#/$defs/port-base
  99. unevaluatedProperties: false
  100. description: Output endpoint of the controller
  101. properties:
  102. endpoint:
  103. $ref: /schemas/media/video-interfaces.yaml#
  104. unevaluatedProperties: false
  105. properties:
  106. data-lanes:
  107. minItems: 1
  108. maxItems: 4
  109. items:
  110. enum: [ 0, 1, 2, 3 ]
  111. link-frequencies:
  112. minItems: 1
  113. maxItems: 4
  114. items:
  115. enum: [ 1620000000, 2700000000, 5400000000, 8100000000 ]
  116. required:
  117. - port@0
  118. - port@1
  119. required:
  120. - compatible
  121. - reg
  122. - interrupts
  123. - clocks
  124. - clock-names
  125. - phys
  126. - phy-names
  127. - power-domains
  128. - ports
  129. allOf:
  130. # AUX BUS does not exist on DP controllers
  131. # Audio output also is present only on DP output
  132. # p1 regions is present on DP, but not on eDP
  133. - if:
  134. properties:
  135. compatible:
  136. contains:
  137. enum:
  138. - qcom,sc7280-edp
  139. - qcom,sc8180x-edp
  140. - qcom,sc8280xp-edp
  141. then:
  142. properties:
  143. "#sound-dai-cells": false
  144. else:
  145. properties:
  146. aux-bus: false
  147. reg:
  148. minItems: 5
  149. required:
  150. - "#sound-dai-cells"
  151. additionalProperties: false
  152. examples:
  153. - |
  154. #include <dt-bindings/interrupt-controller/arm-gic.h>
  155. #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
  156. #include <dt-bindings/power/qcom-rpmpd.h>
  157. displayport-controller@ae90000 {
  158. compatible = "qcom,sc7180-dp";
  159. reg = <0xae90000 0x200>,
  160. <0xae90200 0x200>,
  161. <0xae90400 0xc00>,
  162. <0xae91000 0x400>,
  163. <0xae91400 0x400>;
  164. interrupt-parent = <&mdss>;
  165. interrupts = <12>;
  166. clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
  167. <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
  168. <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
  169. <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
  170. <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
  171. clock-names = "core_iface", "core_aux",
  172. "ctrl_link",
  173. "ctrl_link_iface", "stream_pixel";
  174. assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
  175. <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
  176. assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
  177. phys = <&dp_phy>;
  178. phy-names = "dp";
  179. #sound-dai-cells = <0>;
  180. power-domains = <&rpmhpd SC7180_CX>;
  181. ports {
  182. #address-cells = <1>;
  183. #size-cells = <0>;
  184. port@0 {
  185. reg = <0>;
  186. endpoint {
  187. remote-endpoint = <&dpu_intf0_out>;
  188. };
  189. };
  190. port@1 {
  191. reg = <1>;
  192. endpoint {
  193. remote-endpoint = <&typec>;
  194. data-lanes = <0 1>;
  195. link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
  196. };
  197. };
  198. };
  199. };
  200. ...