mdp4.yaml 2.5 KB

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  1. # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2. %YAML 1.2
  3. ---
  4. $id: http://devicetree.org/schemas/display/msm/mdp4.yaml#
  5. $schema: http://devicetree.org/meta-schemas/core.yaml#
  6. title: Qualcomm Adreno/Snapdragon MDP4 display controller
  7. description: >
  8. MDP4 display controller found in SoCs like MSM8960, APQ8064 and MSM8660.
  9. maintainers:
  10. - Rob Clark <robdclark@gmail.com>
  11. properties:
  12. compatible:
  13. const: qcom,mdp4
  14. clocks:
  15. minItems: 6
  16. maxItems: 6
  17. clock-names:
  18. items:
  19. - const: core_clk
  20. - const: iface_clk
  21. - const: bus_clk
  22. - const: lut_clk
  23. - const: hdmi_clk
  24. - const: tv_clk
  25. reg:
  26. maxItems: 1
  27. interrupts:
  28. maxItems: 1
  29. iommus:
  30. maxItems: 4
  31. ports:
  32. $ref: /schemas/graph.yaml#/properties/ports
  33. properties:
  34. port@0:
  35. $ref: /schemas/graph.yaml#/properties/port
  36. description: LCDC/LVDS
  37. port@1:
  38. $ref: /schemas/graph.yaml#/properties/port
  39. description: DSI1 Cmd / Video
  40. port@2:
  41. $ref: /schemas/graph.yaml#/properties/port
  42. description: DSI2 Cmd / Video
  43. port@3:
  44. $ref: /schemas/graph.yaml#/properties/port
  45. description: Digital TV
  46. qcom,lcdc-align-lsb:
  47. type: boolean
  48. description: >
  49. Indication that LSB alignment should be used for LCDC.
  50. This is only valid for 18bpp panels.
  51. required:
  52. - compatible
  53. - reg
  54. - clocks
  55. - ports
  56. additionalProperties: false
  57. examples:
  58. - |
  59. mdp: mdp@5100000 {
  60. compatible = "qcom,mdp4";
  61. reg = <0x05100000 0xf0000>;
  62. interrupts = <0 75 0>;
  63. clock-names =
  64. "core_clk",
  65. "iface_clk",
  66. "bus_clk",
  67. "lut_clk",
  68. "hdmi_clk",
  69. "tv_clk";
  70. clocks =
  71. <&mmcc 77>,
  72. <&mmcc 86>,
  73. <&mmcc 102>,
  74. <&mmcc 75>,
  75. <&mmcc 97>,
  76. <&mmcc 12>;
  77. ports {
  78. #address-cells = <1>;
  79. #size-cells = <0>;
  80. port@0 {
  81. reg = <0>;
  82. mdp_lvds_out: endpoint {
  83. };
  84. };
  85. port@1 {
  86. reg = <1>;
  87. mdp_dsi1_out: endpoint {
  88. };
  89. };
  90. port@2 {
  91. reg = <2>;
  92. mdp_dsi2_out: endpoint {
  93. };
  94. };
  95. port@3 {
  96. reg = <3>;
  97. mdp_dtv_out: endpoint {
  98. remote-endpoint = <&hdmi_in>;
  99. };
  100. };
  101. };
  102. };