nvidia,tegra20-mpe.yaml 1.3 KB

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  1. # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2. %YAML 1.2
  3. ---
  4. $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-mpe.yaml#
  5. $schema: http://devicetree.org/meta-schemas/core.yaml#
  6. title: NVIDIA Tegra Video Encoder
  7. maintainers:
  8. - Thierry Reding <thierry.reding@gmail.com>
  9. - Jon Hunter <jonathanh@nvidia.com>
  10. properties:
  11. $nodename:
  12. pattern: "^mpe@[0-9a-f]+$"
  13. compatible:
  14. enum:
  15. - nvidia,tegra20-mpe
  16. - nvidia,tegra30-mpe
  17. - nvidia,tegra114-mpe
  18. reg:
  19. maxItems: 1
  20. interrupts:
  21. maxItems: 1
  22. clocks:
  23. items:
  24. - description: module clock
  25. resets:
  26. items:
  27. - description: module reset
  28. reset-names:
  29. items:
  30. - const: mpe
  31. iommus:
  32. maxItems: 1
  33. interconnects:
  34. maxItems: 6
  35. interconnect-names:
  36. maxItems: 6
  37. operating-points-v2: true
  38. power-domains:
  39. items:
  40. - description: phandle to the MPE power domain
  41. additionalProperties: false
  42. examples:
  43. - |
  44. #include <dt-bindings/clock/tegra20-car.h>
  45. #include <dt-bindings/interrupt-controller/arm-gic.h>
  46. mpe@54040000 {
  47. compatible = "nvidia,tegra20-mpe";
  48. reg = <0x54040000 0x00040000>;
  49. interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
  50. clocks = <&tegra_car TEGRA20_CLK_MPE>;
  51. resets = <&tegra_car 60>;
  52. reset-names = "mpe";
  53. };