intel,ixp4xx-network-processing-engine.yaml 2.9 KB

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  1. # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
  2. # Copyright 2019 Linaro Ltd.
  3. %YAML 1.2
  4. ---
  5. $id: http://devicetree.org/schemas/firmware/intel,ixp4xx-network-processing-engine.yaml#
  6. $schema: http://devicetree.org/meta-schemas/core.yaml#
  7. title: Intel IXP4xx Network Processing Engine
  8. maintainers:
  9. - Linus Walleij <linus.walleij@linaro.org>
  10. description: |
  11. On the IXP4xx SoCs, the Network Processing Engine (NPE) is a small
  12. processor that can load a firmware to perform offloading of networking
  13. and crypto tasks. It also manages the MDIO bus to the ethernet PHYs
  14. on the IXP4xx platform. All IXP4xx platforms have three NPEs at
  15. consecutive memory locations. They are all included in the same
  16. device node since they are not independent of each other.
  17. properties:
  18. compatible:
  19. oneOf:
  20. - items:
  21. - const: intel,ixp4xx-network-processing-engine
  22. reg:
  23. items:
  24. - description: NPE0 (NPE-A) register range
  25. - description: NPE1 (NPE-B) register range
  26. - description: NPE2 (NPE-C) register range
  27. crypto:
  28. $ref: /schemas/crypto/intel,ixp4xx-crypto.yaml#
  29. type: object
  30. description: Optional node for the embedded crypto engine, the node
  31. should be named with the instance number of the NPE engine used for
  32. the crypto engine.
  33. "#address-cells":
  34. const: 1
  35. "#size-cells":
  36. const: 0
  37. patternProperties:
  38. hss@[0-9]+$:
  39. $ref: /schemas/net/intel,ixp4xx-hss.yaml#
  40. type: object
  41. description: Optional node for the High Speed Serial link (HSS), the
  42. node should be named with the instance number of the NPE engine
  43. used for the HSS.
  44. required:
  45. - compatible
  46. - reg
  47. additionalProperties: false
  48. examples:
  49. - |
  50. #include <dt-bindings/gpio/gpio.h>
  51. npe: npe@c8006000 {
  52. compatible = "intel,ixp4xx-network-processing-engine";
  53. reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>;
  54. #address-cells = <1>;
  55. #size-cells = <0>;
  56. hss@0 {
  57. compatible = "intel,ixp4xx-hss";
  58. reg = <0>;
  59. intel,npe-handle = <&npe 0>;
  60. intel,queue-chl-rxtrig = <&qmgr 12>;
  61. intel,queue-chl-txready = <&qmgr 34>;
  62. intel,queue-pkt-rx = <&qmgr 13>;
  63. intel,queue-pkt-tx = <&qmgr 14>, <&qmgr 15>, <&qmgr 16>, <&qmgr 17>;
  64. intel,queue-pkt-rxfree = <&qmgr 18>, <&qmgr 19>, <&qmgr 20>, <&qmgr 21>;
  65. intel,queue-pkt-txdone = <&qmgr 22>;
  66. cts-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
  67. rts-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
  68. dcd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
  69. dtr-gpios = <&gpio_74 2 GPIO_ACTIVE_LOW>;
  70. clk-internal-gpios = <&gpio_74 0 GPIO_ACTIVE_HIGH>;
  71. };
  72. crypto {
  73. compatible = "intel,ixp4xx-crypto";
  74. intel,npe-handle = <&npe 2>;
  75. queue-rx = <&qmgr 30>;
  76. queue-txready = <&qmgr 29>;
  77. };
  78. };
  79. ...