rockchip,iommu.yaml 2.0 KB

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  1. # SPDX-License-Identifier: GPL-2.0-only
  2. %YAML 1.2
  3. ---
  4. $id: http://devicetree.org/schemas/iommu/rockchip,iommu.yaml#
  5. $schema: http://devicetree.org/meta-schemas/core.yaml#
  6. title: Rockchip IOMMU
  7. maintainers:
  8. - Heiko Stuebner <heiko@sntech.de>
  9. description: |+
  10. A Rockchip DRM iommu translates io virtual addresses to physical addresses for
  11. its master device. Each slave device is bound to a single master device and
  12. shares its clocks, power domain and irq.
  13. For information on assigning IOMMU controller to its peripheral devices,
  14. see generic IOMMU bindings.
  15. properties:
  16. compatible:
  17. oneOf:
  18. - enum:
  19. - rockchip,iommu
  20. - rockchip,rk3568-iommu
  21. - items:
  22. - enum:
  23. - rockchip,rk3588-iommu
  24. - const: rockchip,rk3568-iommu
  25. reg:
  26. items:
  27. - description: configuration registers for MMU instance 0
  28. - description: configuration registers for MMU instance 1
  29. minItems: 1
  30. interrupts:
  31. items:
  32. - description: interruption for MMU instance 0
  33. - description: interruption for MMU instance 1
  34. minItems: 1
  35. clocks:
  36. items:
  37. - description: Core clock
  38. - description: Interface clock
  39. clock-names:
  40. items:
  41. - const: aclk
  42. - const: iface
  43. "#iommu-cells":
  44. const: 0
  45. power-domains:
  46. maxItems: 1
  47. rockchip,disable-mmu-reset:
  48. $ref: /schemas/types.yaml#/definitions/flag
  49. description: |
  50. Do not use the mmu reset operation.
  51. Some mmu instances may produce unexpected results
  52. when the reset operation is used.
  53. required:
  54. - compatible
  55. - reg
  56. - interrupts
  57. - clocks
  58. - clock-names
  59. - "#iommu-cells"
  60. additionalProperties: false
  61. examples:
  62. - |
  63. #include <dt-bindings/clock/rk3399-cru.h>
  64. #include <dt-bindings/interrupt-controller/arm-gic.h>
  65. vopl_mmu: iommu@ff940300 {
  66. compatible = "rockchip,iommu";
  67. reg = <0xff940300 0x100>;
  68. interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
  69. clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
  70. clock-names = "aclk", "iface";
  71. #iommu-cells = <0>;
  72. };