calxeda-ddr-ctrlr.yaml 913 B

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  1. # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2. %YAML 1.2
  3. ---
  4. $id: http://devicetree.org/schemas/memory-controllers/calxeda-ddr-ctrlr.yaml#
  5. $schema: http://devicetree.org/meta-schemas/core.yaml#
  6. title: Calxeda DDR memory controller
  7. description: |
  8. The Calxeda DDR memory controller is initialised and programmed by the
  9. firmware, but an OS might want to read its registers for error reporting
  10. purposes and to learn about the DRAM topology.
  11. maintainers:
  12. - Andre Przywara <andre.przywara@arm.com>
  13. properties:
  14. compatible:
  15. enum:
  16. - calxeda,hb-ddr-ctrl
  17. - calxeda,ecx-2000-ddr-ctrl
  18. reg:
  19. maxItems: 1
  20. interrupts:
  21. maxItems: 1
  22. required:
  23. - compatible
  24. - reg
  25. - interrupts
  26. additionalProperties: false
  27. examples:
  28. - |
  29. memory-controller@fff00000 {
  30. compatible = "calxeda,hb-ddr-ctrl";
  31. reg = <0xfff00000 0x1000>;
  32. interrupts = <0 91 4>;
  33. };