xlnx,zynqmp-ocmc-1.0.yaml 1.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445
  1. # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
  2. %YAML 1.2
  3. ---
  4. $id: http://devicetree.org/schemas/memory-controllers/xlnx,zynqmp-ocmc-1.0.yaml#
  5. $schema: http://devicetree.org/meta-schemas/core.yaml#
  6. title: Xilinx Zynqmp OCM(On-Chip Memory) Controller
  7. maintainers:
  8. - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
  9. - Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
  10. description: |
  11. The OCM supports 64-bit wide ECC functionality to detect multi-bit errors
  12. and recover from a single-bit memory fault.On a write, if all bytes are
  13. being written, the ECC is generated and written into the ECC RAM along with
  14. the write-data that is written into the data RAM. If one or more bytes are
  15. not written, then the read operation results in an correctable error or
  16. uncorrectable error.
  17. properties:
  18. compatible:
  19. const: xlnx,zynqmp-ocmc-1.0
  20. reg:
  21. maxItems: 1
  22. interrupts:
  23. maxItems: 1
  24. required:
  25. - compatible
  26. - reg
  27. - interrupts
  28. additionalProperties: false
  29. examples:
  30. - |
  31. #include <dt-bindings/interrupt-controller/arm-gic.h>
  32. memory-controller@ff960000 {
  33. compatible = "xlnx,zynqmp-ocmc-1.0";
  34. reg = <0xff960000 0x1000>;
  35. interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
  36. };