qcom,sc7180-mss-pil.yaml 6.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247
  1. # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2. %YAML 1.2
  3. ---
  4. $id: http://devicetree.org/schemas/remoteproc/qcom,sc7180-mss-pil.yaml#
  5. $schema: http://devicetree.org/meta-schemas/core.yaml#
  6. title: Qualcomm SC7180 MSS Peripheral Image Loader
  7. maintainers:
  8. - Sibi Sankar <quic_sibis@quicinc.com>
  9. description:
  10. This document describes the hardware for a component that loads and boots firmware
  11. on the Qualcomm Technology Inc. SC7180 Modem Hexagon Core.
  12. properties:
  13. compatible:
  14. enum:
  15. - qcom,sc7180-mss-pil
  16. reg:
  17. items:
  18. - description: MSS QDSP6 registers
  19. - description: RMB registers
  20. reg-names:
  21. items:
  22. - const: qdsp6
  23. - const: rmb
  24. iommus:
  25. items:
  26. - description: MSA Stream 1
  27. - description: MSA Stream 2
  28. interrupts:
  29. items:
  30. - description: Watchdog interrupt
  31. - description: Fatal interrupt
  32. - description: Ready interrupt
  33. - description: Handover interrupt
  34. - description: Stop acknowledge interrupt
  35. - description: Shutdown acknowledge interrupt
  36. interrupt-names:
  37. items:
  38. - const: wdog
  39. - const: fatal
  40. - const: ready
  41. - const: handover
  42. - const: stop-ack
  43. - const: shutdown-ack
  44. clocks:
  45. items:
  46. - description: GCC MSS IFACE clock
  47. - description: GCC MSS BUS clock
  48. - description: GCC MSS NAV clock
  49. - description: GCC MSS SNOC_AXI clock
  50. - description: GCC MSS MFAB_AXIS clock
  51. - description: RPMH XO clock
  52. clock-names:
  53. items:
  54. - const: iface
  55. - const: bus
  56. - const: nav
  57. - const: snoc_axi
  58. - const: mnoc_axi
  59. - const: xo
  60. power-domains:
  61. items:
  62. - description: CX power domain
  63. - description: MX power domain
  64. - description: MSS power domain
  65. power-domain-names:
  66. items:
  67. - const: cx
  68. - const: mx
  69. - const: mss
  70. resets:
  71. items:
  72. - description: AOSS restart
  73. - description: PDC reset
  74. reset-names:
  75. items:
  76. - const: mss_restart
  77. - const: pdc_reset
  78. memory-region:
  79. items:
  80. - description: MBA reserved region
  81. - description: modem reserved region
  82. - description: metadata reserved region
  83. firmware-name:
  84. $ref: /schemas/types.yaml#/definitions/string-array
  85. items:
  86. - description: Name of MBA firmware
  87. - description: Name of modem firmware
  88. qcom,halt-regs:
  89. $ref: /schemas/types.yaml#/definitions/phandle-array
  90. description:
  91. Halt registers are used to halt transactions of various sub-components
  92. within MSS.
  93. items:
  94. - items:
  95. - description: phandle to TCSR_MUTEX registers
  96. - description: offset to the Q6 halt register
  97. - description: offset to the modem halt register
  98. - description: offset to the nc halt register
  99. qcom,spare-regs:
  100. $ref: /schemas/types.yaml#/definitions/phandle-array
  101. description:
  102. Spare registers are multipurpose registers used for errata
  103. handling.
  104. items:
  105. - items:
  106. - description: phandle to TCSR_MUTEX registers
  107. - description: offset to the conn_box_spare0 register
  108. qcom,qmp:
  109. $ref: /schemas/types.yaml#/definitions/phandle
  110. description: Reference to the AOSS side-channel message RAM.
  111. qcom,smem-states:
  112. $ref: /schemas/types.yaml#/definitions/phandle-array
  113. description: States used by the AP to signal the Hexagon core
  114. items:
  115. - description: Stop the modem
  116. qcom,smem-state-names:
  117. description: The names of the state bits used for SMP2P output
  118. const: stop
  119. glink-edge:
  120. $ref: qcom,glink-edge.yaml#
  121. unevaluatedProperties: false
  122. description:
  123. Qualcomm G-Link subnode which represents communication edge, channels
  124. and devices related to the DSP.
  125. properties:
  126. interrupts:
  127. items:
  128. - description: IRQ from MSS to GLINK
  129. mboxes:
  130. items:
  131. - description: Mailbox for communication between APPS and MSS
  132. label:
  133. const: modem
  134. apr: false
  135. fastrpc: false
  136. required:
  137. - compatible
  138. - reg
  139. - reg-names
  140. - iommus
  141. - interrupts
  142. - interrupt-names
  143. - clocks
  144. - clock-names
  145. - power-domains
  146. - power-domain-names
  147. - resets
  148. - reset-names
  149. - qcom,halt-regs
  150. - qcom,spare-regs
  151. - memory-region
  152. - qcom,qmp
  153. - qcom,smem-states
  154. - qcom,smem-state-names
  155. - glink-edge
  156. additionalProperties: false
  157. examples:
  158. - |
  159. #include <dt-bindings/clock/qcom,gcc-sc7180.h>
  160. #include <dt-bindings/clock/qcom,rpmh.h>
  161. #include <dt-bindings/interrupt-controller/arm-gic.h>
  162. #include <dt-bindings/power/qcom-rpmpd.h>
  163. #include <dt-bindings/reset/qcom,sdm845-aoss.h>
  164. #include <dt-bindings/reset/qcom,sdm845-pdc.h>
  165. remoteproc_mpss: remoteproc@4080000 {
  166. compatible = "qcom,sc7180-mss-pil";
  167. reg = <0x04080000 0x10000>, <0x04180000 0x48>;
  168. reg-names = "qdsp6", "rmb";
  169. iommus = <&apps_smmu 0x461 0x0>, <&apps_smmu 0x444 0x3>;
  170. interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
  171. <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
  172. <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
  173. <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
  174. <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
  175. <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
  176. interrupt-names = "wdog", "fatal", "ready", "handover",
  177. "stop-ack", "shutdown-ack";
  178. clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
  179. <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
  180. <&gcc GCC_MSS_NAV_AXI_CLK>,
  181. <&gcc GCC_MSS_SNOC_AXI_CLK>,
  182. <&gcc GCC_MSS_MFAB_AXIS_CLK>,
  183. <&rpmhcc RPMH_CXO_CLK>;
  184. clock-names = "iface", "bus", "nav", "snoc_axi",
  185. "mnoc_axi", "xo";
  186. power-domains = <&rpmhpd SC7180_CX>,
  187. <&rpmhpd SC7180_MX>,
  188. <&rpmhpd SC7180_MSS>;
  189. power-domain-names = "cx", "mx", "mss";
  190. memory-region = <&mba_mem>, <&mpss_mem>, <&mdata_mem>;
  191. qcom,qmp = <&aoss_qmp>;
  192. qcom,smem-states = <&modem_smp2p_out 0>;
  193. qcom,smem-state-names = "stop";
  194. resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
  195. <&pdc_reset PDC_MODEM_SYNC_RESET>;
  196. reset-names = "mss_restart", "pdc_reset";
  197. qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
  198. qcom,spare-regs = <&tcsr_regs 0xb3e4>;
  199. glink-edge {
  200. interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
  201. mboxes = <&apss_shared 12>;
  202. qcom,remote-pid = <1>;
  203. label = "modem";
  204. };
  205. };