qcom,dwc3.yaml 16 KB

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  1. # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
  2. %YAML 1.2
  3. ---
  4. $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml#
  5. $schema: http://devicetree.org/meta-schemas/core.yaml#
  6. title: Qualcomm SuperSpeed DWC3 USB SoC controller
  7. maintainers:
  8. - Wesley Cheng <quic_wcheng@quicinc.com>
  9. properties:
  10. compatible:
  11. items:
  12. - enum:
  13. - qcom,ipq4019-dwc3
  14. - qcom,ipq5018-dwc3
  15. - qcom,ipq5332-dwc3
  16. - qcom,ipq6018-dwc3
  17. - qcom,ipq8064-dwc3
  18. - qcom,ipq8074-dwc3
  19. - qcom,ipq9574-dwc3
  20. - qcom,msm8953-dwc3
  21. - qcom,msm8994-dwc3
  22. - qcom,msm8996-dwc3
  23. - qcom,msm8998-dwc3
  24. - qcom,qcm2290-dwc3
  25. - qcom,qcs404-dwc3
  26. - qcom,qdu1000-dwc3
  27. - qcom,sa8775p-dwc3
  28. - qcom,sc7180-dwc3
  29. - qcom,sc7280-dwc3
  30. - qcom,sc8180x-dwc3
  31. - qcom,sc8180x-dwc3-mp
  32. - qcom,sc8280xp-dwc3
  33. - qcom,sc8280xp-dwc3-mp
  34. - qcom,sdm660-dwc3
  35. - qcom,sdm670-dwc3
  36. - qcom,sdm845-dwc3
  37. - qcom,sdx55-dwc3
  38. - qcom,sdx65-dwc3
  39. - qcom,sdx75-dwc3
  40. - qcom,sm4250-dwc3
  41. - qcom,sm6115-dwc3
  42. - qcom,sm6125-dwc3
  43. - qcom,sm6350-dwc3
  44. - qcom,sm6375-dwc3
  45. - qcom,sm8150-dwc3
  46. - qcom,sm8250-dwc3
  47. - qcom,sm8350-dwc3
  48. - qcom,sm8450-dwc3
  49. - qcom,sm8550-dwc3
  50. - qcom,sm8650-dwc3
  51. - qcom,x1e80100-dwc3
  52. - qcom,x1e80100-dwc3-mp
  53. - const: qcom,dwc3
  54. reg:
  55. description: Offset and length of register set for QSCRATCH wrapper
  56. maxItems: 1
  57. "#address-cells":
  58. enum: [ 1, 2 ]
  59. "#size-cells":
  60. enum: [ 1, 2 ]
  61. ranges: true
  62. power-domains:
  63. description: specifies a phandle to PM domain provider node
  64. maxItems: 1
  65. required-opps:
  66. maxItems: 1
  67. clocks:
  68. description: |
  69. Several clocks are used, depending on the variant. Typical ones are::
  70. - cfg_noc:: System Config NOC clock.
  71. - core:: Master/Core clock, has to be >= 125 MHz for SS operation and >=
  72. 60MHz for HS operation.
  73. - iface:: System bus AXI clock.
  74. - sleep:: Sleep clock, used for wakeup when USB3 core goes into low
  75. power mode (U3).
  76. - mock_utmi:: Mock utmi clock needed for ITP/SOF generation in host
  77. mode. Its frequency should be 19.2MHz.
  78. minItems: 1
  79. maxItems: 9
  80. clock-names:
  81. minItems: 1
  82. maxItems: 9
  83. resets:
  84. maxItems: 1
  85. interconnects:
  86. maxItems: 2
  87. interconnect-names:
  88. items:
  89. - const: usb-ddr
  90. - const: apps-usb
  91. interrupts:
  92. description: |
  93. Different types of interrupts are used based on HS PHY used on target:
  94. - pwr_event: Used for wakeup based on other power events.
  95. - hs_phy_irq: Apart from DP/DM/QUSB2 PHY interrupts, there is
  96. hs_phy_irq which is not triggered by default and its
  97. functionality is mutually exclusive to that of
  98. {dp/dm}_hs_phy_irq and qusb2_phy_irq.
  99. - qusb2_phy: SoCs with QUSB2 PHY do not have separate DP/DM IRQs and
  100. expose only a single IRQ whose behavior can be modified
  101. by the QUSB2PHY_INTR_CTRL register. The required DPSE/
  102. DMSE configuration is done in QUSB2PHY_INTR_CTRL register
  103. of PHY address space.
  104. - {dp/dm}_hs_phy_irq: These IRQ's directly reflect changes on the DP/
  105. DM pads of the SoC. These are used for wakeup
  106. only on SoCs with non-QUSB2 targets with
  107. exception of SDM670/SDM845/SM6350.
  108. - ss_phy_irq: Used for remote wakeup in Super Speed mode of operation.
  109. minItems: 2
  110. maxItems: 18
  111. interrupt-names:
  112. minItems: 2
  113. maxItems: 18
  114. qcom,select-utmi-as-pipe-clk:
  115. description:
  116. If present, disable USB3 pipe_clk requirement.
  117. Used when dwc3 operates without SSPHY and only
  118. HS/FS/LS modes are supported.
  119. type: boolean
  120. wakeup-source: true
  121. # Required child node:
  122. patternProperties:
  123. "^usb@[0-9a-f]+$":
  124. $ref: snps,dwc3.yaml#
  125. unevaluatedProperties: false
  126. properties:
  127. wakeup-source: false
  128. required:
  129. - compatible
  130. - reg
  131. - "#address-cells"
  132. - "#size-cells"
  133. - ranges
  134. - clocks
  135. - clock-names
  136. - interrupts
  137. - interrupt-names
  138. allOf:
  139. - if:
  140. properties:
  141. compatible:
  142. contains:
  143. enum:
  144. - qcom,ipq4019-dwc3
  145. - qcom,ipq5332-dwc3
  146. then:
  147. properties:
  148. clocks:
  149. maxItems: 3
  150. clock-names:
  151. items:
  152. - const: core
  153. - const: sleep
  154. - const: mock_utmi
  155. - if:
  156. properties:
  157. compatible:
  158. contains:
  159. enum:
  160. - qcom,ipq8064-dwc3
  161. then:
  162. properties:
  163. clocks:
  164. items:
  165. - description: Master/Core clock, has to be >= 125 MHz
  166. for SS operation and >= 60MHz for HS operation.
  167. clock-names:
  168. items:
  169. - const: core
  170. - if:
  171. properties:
  172. compatible:
  173. contains:
  174. enum:
  175. - qcom,ipq9574-dwc3
  176. - qcom,msm8953-dwc3
  177. - qcom,msm8996-dwc3
  178. - qcom,msm8998-dwc3
  179. - qcom,sa8775p-dwc3
  180. - qcom,sc7180-dwc3
  181. - qcom,sc7280-dwc3
  182. - qcom,sdm670-dwc3
  183. - qcom,sdm845-dwc3
  184. - qcom,sdx55-dwc3
  185. - qcom,sdx65-dwc3
  186. - qcom,sdx75-dwc3
  187. - qcom,sm6350-dwc3
  188. then:
  189. properties:
  190. clocks:
  191. maxItems: 5
  192. clock-names:
  193. items:
  194. - const: cfg_noc
  195. - const: core
  196. - const: iface
  197. - const: sleep
  198. - const: mock_utmi
  199. - if:
  200. properties:
  201. compatible:
  202. contains:
  203. enum:
  204. - qcom,ipq6018-dwc3
  205. then:
  206. properties:
  207. clocks:
  208. minItems: 3
  209. maxItems: 4
  210. clock-names:
  211. oneOf:
  212. - items:
  213. - const: core
  214. - const: sleep
  215. - const: mock_utmi
  216. - items:
  217. - const: cfg_noc
  218. - const: core
  219. - const: sleep
  220. - const: mock_utmi
  221. - if:
  222. properties:
  223. compatible:
  224. contains:
  225. enum:
  226. - qcom,ipq8074-dwc3
  227. - qcom,qdu1000-dwc3
  228. then:
  229. properties:
  230. clocks:
  231. maxItems: 4
  232. clock-names:
  233. items:
  234. - const: cfg_noc
  235. - const: core
  236. - const: sleep
  237. - const: mock_utmi
  238. - if:
  239. properties:
  240. compatible:
  241. contains:
  242. enum:
  243. - qcom,ipq5018-dwc3
  244. - qcom,msm8994-dwc3
  245. - qcom,qcs404-dwc3
  246. then:
  247. properties:
  248. clocks:
  249. maxItems: 4
  250. clock-names:
  251. items:
  252. - const: core
  253. - const: iface
  254. - const: sleep
  255. - const: mock_utmi
  256. - if:
  257. properties:
  258. compatible:
  259. contains:
  260. enum:
  261. - qcom,sc8280xp-dwc3
  262. - qcom,sc8280xp-dwc3-mp
  263. - qcom,x1e80100-dwc3
  264. - qcom,x1e80100-dwc3-mp
  265. then:
  266. properties:
  267. clocks:
  268. maxItems: 9
  269. clock-names:
  270. items:
  271. - const: cfg_noc
  272. - const: core
  273. - const: iface
  274. - const: sleep
  275. - const: mock_utmi
  276. - const: noc_aggr
  277. - const: noc_aggr_north
  278. - const: noc_aggr_south
  279. - const: noc_sys
  280. - if:
  281. properties:
  282. compatible:
  283. contains:
  284. enum:
  285. - qcom,sdm660-dwc3
  286. then:
  287. properties:
  288. clocks:
  289. minItems: 4
  290. maxItems: 5
  291. clock-names:
  292. oneOf:
  293. - items:
  294. - const: cfg_noc
  295. - const: core
  296. - const: iface
  297. - const: sleep
  298. - const: mock_utmi
  299. - items:
  300. - const: cfg_noc
  301. - const: core
  302. - const: sleep
  303. - const: mock_utmi
  304. - if:
  305. properties:
  306. compatible:
  307. contains:
  308. enum:
  309. - qcom,qcm2290-dwc3
  310. - qcom,sc8180x-dwc3
  311. - qcom,sc8180x-dwc3-mp
  312. - qcom,sm6115-dwc3
  313. - qcom,sm6125-dwc3
  314. - qcom,sm8150-dwc3
  315. - qcom,sm8250-dwc3
  316. - qcom,sm8450-dwc3
  317. - qcom,sm8550-dwc3
  318. - qcom,sm8650-dwc3
  319. then:
  320. properties:
  321. clocks:
  322. minItems: 6
  323. clock-names:
  324. items:
  325. - const: cfg_noc
  326. - const: core
  327. - const: iface
  328. - const: sleep
  329. - const: mock_utmi
  330. - const: xo
  331. - if:
  332. properties:
  333. compatible:
  334. contains:
  335. enum:
  336. - qcom,sm8350-dwc3
  337. then:
  338. properties:
  339. clocks:
  340. minItems: 5
  341. maxItems: 6
  342. clock-names:
  343. minItems: 5
  344. items:
  345. - const: cfg_noc
  346. - const: core
  347. - const: iface
  348. - const: sleep
  349. - const: mock_utmi
  350. - const: xo
  351. - if:
  352. properties:
  353. compatible:
  354. contains:
  355. enum:
  356. - qcom,ipq5018-dwc3
  357. - qcom,ipq6018-dwc3
  358. - qcom,ipq8074-dwc3
  359. - qcom,msm8953-dwc3
  360. - qcom,msm8998-dwc3
  361. then:
  362. properties:
  363. interrupts:
  364. minItems: 2
  365. maxItems: 3
  366. interrupt-names:
  367. items:
  368. - const: pwr_event
  369. - const: qusb2_phy
  370. - const: ss_phy_irq
  371. - if:
  372. properties:
  373. compatible:
  374. contains:
  375. enum:
  376. - qcom,msm8996-dwc3
  377. - qcom,qcs404-dwc3
  378. - qcom,sdm660-dwc3
  379. - qcom,sm6115-dwc3
  380. - qcom,sm6125-dwc3
  381. then:
  382. properties:
  383. interrupts:
  384. minItems: 3
  385. maxItems: 4
  386. interrupt-names:
  387. items:
  388. - const: pwr_event
  389. - const: qusb2_phy
  390. - const: hs_phy_irq
  391. - const: ss_phy_irq
  392. - if:
  393. properties:
  394. compatible:
  395. contains:
  396. enum:
  397. - qcom,ipq5332-dwc3
  398. then:
  399. properties:
  400. interrupts:
  401. maxItems: 3
  402. interrupt-names:
  403. items:
  404. - const: pwr_event
  405. - const: dp_hs_phy_irq
  406. - const: dm_hs_phy_irq
  407. - if:
  408. properties:
  409. compatible:
  410. contains:
  411. enum:
  412. - qcom,x1e80100-dwc3
  413. then:
  414. properties:
  415. interrupts:
  416. maxItems: 4
  417. interrupt-names:
  418. items:
  419. - const: pwr_event
  420. - const: dp_hs_phy_irq
  421. - const: dm_hs_phy_irq
  422. - const: ss_phy_irq
  423. - if:
  424. properties:
  425. compatible:
  426. contains:
  427. enum:
  428. - qcom,ipq4019-dwc3
  429. - qcom,ipq8064-dwc3
  430. - qcom,msm8994-dwc3
  431. - qcom,qdu1000-dwc3
  432. - qcom,sa8775p-dwc3
  433. - qcom,sc7180-dwc3
  434. - qcom,sc7280-dwc3
  435. - qcom,sc8180x-dwc3
  436. - qcom,sc8280xp-dwc3
  437. - qcom,sdm670-dwc3
  438. - qcom,sdm845-dwc3
  439. - qcom,sdx55-dwc3
  440. - qcom,sdx65-dwc3
  441. - qcom,sdx75-dwc3
  442. - qcom,sm4250-dwc3
  443. - qcom,sm6350-dwc3
  444. - qcom,sm8150-dwc3
  445. - qcom,sm8250-dwc3
  446. - qcom,sm8350-dwc3
  447. - qcom,sm8450-dwc3
  448. - qcom,sm8550-dwc3
  449. - qcom,sm8650-dwc3
  450. then:
  451. properties:
  452. interrupts:
  453. minItems: 4
  454. maxItems: 5
  455. interrupt-names:
  456. items:
  457. - const: pwr_event
  458. - const: hs_phy_irq
  459. - const: dp_hs_phy_irq
  460. - const: dm_hs_phy_irq
  461. - const: ss_phy_irq
  462. - if:
  463. properties:
  464. compatible:
  465. contains:
  466. enum:
  467. - qcom,sc8180x-dwc3-mp
  468. - qcom,x1e80100-dwc3-mp
  469. then:
  470. properties:
  471. interrupts:
  472. minItems: 10
  473. maxItems: 10
  474. interrupt-names:
  475. items:
  476. - const: pwr_event_1
  477. - const: pwr_event_2
  478. - const: hs_phy_1
  479. - const: hs_phy_2
  480. - const: dp_hs_phy_1
  481. - const: dm_hs_phy_1
  482. - const: dp_hs_phy_2
  483. - const: dm_hs_phy_2
  484. - const: ss_phy_1
  485. - const: ss_phy_2
  486. - if:
  487. properties:
  488. compatible:
  489. contains:
  490. enum:
  491. - qcom,sc8280xp-dwc3-mp
  492. then:
  493. properties:
  494. interrupts:
  495. minItems: 18
  496. maxItems: 18
  497. interrupt-names:
  498. items:
  499. - const: pwr_event_1
  500. - const: pwr_event_2
  501. - const: pwr_event_3
  502. - const: pwr_event_4
  503. - const: hs_phy_1
  504. - const: hs_phy_2
  505. - const: hs_phy_3
  506. - const: hs_phy_4
  507. - const: dp_hs_phy_1
  508. - const: dm_hs_phy_1
  509. - const: dp_hs_phy_2
  510. - const: dm_hs_phy_2
  511. - const: dp_hs_phy_3
  512. - const: dm_hs_phy_3
  513. - const: dp_hs_phy_4
  514. - const: dm_hs_phy_4
  515. - const: ss_phy_1
  516. - const: ss_phy_2
  517. additionalProperties: false
  518. examples:
  519. - |
  520. #include <dt-bindings/clock/qcom,gcc-sdm845.h>
  521. #include <dt-bindings/interrupt-controller/arm-gic.h>
  522. #include <dt-bindings/interrupt-controller/irq.h>
  523. soc {
  524. #address-cells = <2>;
  525. #size-cells = <2>;
  526. usb@a6f8800 {
  527. compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
  528. reg = <0 0x0a6f8800 0 0x400>;
  529. #address-cells = <2>;
  530. #size-cells = <2>;
  531. ranges;
  532. clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
  533. <&gcc GCC_USB30_PRIM_MASTER_CLK>,
  534. <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
  535. <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
  536. <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
  537. clock-names = "cfg_noc",
  538. "core",
  539. "iface",
  540. "sleep",
  541. "mock_utmi";
  542. assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
  543. <&gcc GCC_USB30_PRIM_MASTER_CLK>;
  544. assigned-clock-rates = <19200000>, <150000000>;
  545. interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
  546. <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
  547. <GIC_SPI 489 IRQ_TYPE_EDGE_BOTH>,
  548. <GIC_SPI 488 IRQ_TYPE_EDGE_BOTH>,
  549. <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>;
  550. interrupt-names = "pwr_event", "hs_phy_irq",
  551. "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq";
  552. power-domains = <&gcc USB30_PRIM_GDSC>;
  553. resets = <&gcc GCC_USB30_PRIM_BCR>;
  554. usb@a600000 {
  555. compatible = "snps,dwc3";
  556. reg = <0 0x0a600000 0 0xcd00>;
  557. interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
  558. iommus = <&apps_smmu 0x740 0>;
  559. snps,dis_u2_susphy_quirk;
  560. snps,dis_enblslpm_quirk;
  561. phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
  562. phy-names = "usb2-phy", "usb3-phy";
  563. };
  564. };
  565. };