chromeos-acpi-device.rst 8.7 KB

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  1. .. SPDX-License-Identifier: GPL-2.0
  2. =====================
  3. Chrome OS ACPI Device
  4. =====================
  5. Hardware functionality specific to Chrome OS is exposed through a Chrome OS ACPI device.
  6. The plug and play ID of a Chrome OS ACPI device is GGL0001 and the hardware ID is
  7. GOOG0016. The following ACPI objects are supported:
  8. .. flat-table:: Supported ACPI Objects
  9. :widths: 1 2
  10. :header-rows: 1
  11. * - Object
  12. - Description
  13. * - CHSW
  14. - Chrome OS switch positions
  15. * - HWID
  16. - Chrome OS hardware ID
  17. * - FWID
  18. - Chrome OS firmware version
  19. * - FRID
  20. - Chrome OS read-only firmware version
  21. * - BINF
  22. - Chrome OS boot information
  23. * - GPIO
  24. - Chrome OS GPIO assignments
  25. * - VBNV
  26. - Chrome OS NVRAM locations
  27. * - VDTA
  28. - Chrome OS verified boot data
  29. * - FMAP
  30. - Chrome OS flashmap base address
  31. * - MLST
  32. - Chrome OS method list
  33. CHSW (Chrome OS switch positions)
  34. =================================
  35. This control method returns the switch positions for Chrome OS specific hardware switches.
  36. Arguments:
  37. ----------
  38. None
  39. Result code:
  40. ------------
  41. An integer containing the switch positions as bitfields:
  42. .. flat-table::
  43. :widths: 1 2
  44. * - 0x00000002
  45. - Recovery button was pressed when x86 firmware booted.
  46. * - 0x00000004
  47. - Recovery button was pressed when EC firmware booted. (required if EC EEPROM is
  48. rewritable; otherwise optional)
  49. * - 0x00000020
  50. - Developer switch was enabled when x86 firmware booted.
  51. * - 0x00000200
  52. - Firmware write protection was disabled when x86 firmware booted. (required if
  53. firmware write protection is controlled through x86 BIOS; otherwise optional)
  54. All other bits are reserved and should be set to 0.
  55. HWID (Chrome OS hardware ID)
  56. ============================
  57. This control method returns the hardware ID for the Chromebook.
  58. Arguments:
  59. ----------
  60. None
  61. Result code:
  62. ------------
  63. A null-terminated ASCII string containing the hardware ID from the Model-Specific Data area of
  64. EEPROM.
  65. Note that the hardware ID can be up to 256 characters long, including the terminating null.
  66. FWID (Chrome OS firmware version)
  67. =================================
  68. This control method returns the firmware version for the rewritable portion of the main
  69. processor firmware.
  70. Arguments:
  71. ----------
  72. None
  73. Result code:
  74. ------------
  75. A null-terminated ASCII string containing the complete firmware version for the rewritable
  76. portion of the main processor firmware.
  77. FRID (Chrome OS read-only firmware version)
  78. ===========================================
  79. This control method returns the firmware version for the read-only portion of the main
  80. processor firmware.
  81. Arguments:
  82. ----------
  83. None
  84. Result code:
  85. ------------
  86. A null-terminated ASCII string containing the complete firmware version for the read-only
  87. (bootstrap + recovery ) portion of the main processor firmware.
  88. BINF (Chrome OS boot information)
  89. =================================
  90. This control method returns information about the current boot.
  91. Arguments:
  92. ----------
  93. None
  94. Result code:
  95. ------------
  96. .. code-block::
  97. Package {
  98. Reserved1
  99. Reserved2
  100. Active EC Firmware
  101. Active Main Firmware Type
  102. Reserved5
  103. }
  104. .. flat-table::
  105. :widths: 1 1 2
  106. :header-rows: 1
  107. * - Field
  108. - Format
  109. - Description
  110. * - Reserved1
  111. - DWORD
  112. - Set to 256 (0x100). This indicates this field is no longer used.
  113. * - Reserved2
  114. - DWORD
  115. - Set to 256 (0x100). This indicates this field is no longer used.
  116. * - Active EC firmware
  117. - DWORD
  118. - The EC firmware which was used during boot.
  119. - 0 - Read-only (recovery) firmware
  120. - 1 - Rewritable firmware.
  121. Set to 0 if EC firmware is always read-only.
  122. * - Active Main Firmware Type
  123. - DWORD
  124. - The main firmware type which was used during boot.
  125. - 0 - Recovery
  126. - 1 - Normal
  127. - 2 - Developer
  128. - 3 - netboot (factory installation only)
  129. Other values are reserved.
  130. * - Reserved5
  131. - DWORD
  132. - Set to 256 (0x100). This indicates this field is no longer used.
  133. GPIO (Chrome OS GPIO assignments)
  134. =================================
  135. This control method returns information about Chrome OS specific GPIO assignments for
  136. Chrome OS hardware, so the kernel can directly control that hardware.
  137. Arguments:
  138. ----------
  139. None
  140. Result code:
  141. ------------
  142. .. code-block::
  143. Package {
  144. Package {
  145. // First GPIO assignment
  146. Signal Type //DWORD
  147. Attributes //DWORD
  148. Controller Offset //DWORD
  149. Controller Name //ASCIIZ
  150. },
  151. ...
  152. Package {
  153. // Last GPIO assignment
  154. Signal Type //DWORD
  155. Attributes //DWORD
  156. Controller Offset //DWORD
  157. Controller Name //ASCIIZ
  158. }
  159. }
  160. Where ASCIIZ means a null-terminated ASCII string.
  161. .. flat-table::
  162. :widths: 1 1 2
  163. :header-rows: 1
  164. * - Field
  165. - Format
  166. - Description
  167. * - Signal Type
  168. - DWORD
  169. - Type of GPIO signal
  170. - 0x00000001 - Recovery button
  171. - 0x00000002 - Developer mode switch
  172. - 0x00000003 - Firmware write protection switch
  173. - 0x00000100 - Debug header GPIO 0
  174. - ...
  175. - 0x000001FF - Debug header GPIO 255
  176. Other values are reserved.
  177. * - Attributes
  178. - DWORD
  179. - Signal attributes as bitfields:
  180. - 0x00000001 - Signal is active-high (for button, a GPIO value
  181. of 1 means the button is pressed; for switches, a GPIO value
  182. of 1 means the switch is enabled). If this bit is 0, the signal
  183. is active low. Set to 0 for debug header GPIOs.
  184. * - Controller Offset
  185. - DWORD
  186. - GPIO number on the specified controller.
  187. * - Controller Name
  188. - ASCIIZ
  189. - Name of the controller for the GPIO.
  190. Currently supported names:
  191. "NM10" - Intel NM10 chip
  192. VBNV (Chrome OS NVRAM locations)
  193. ================================
  194. This control method returns information about the NVRAM (CMOS) locations used to
  195. communicate with the BIOS.
  196. Arguments:
  197. ----------
  198. None
  199. Result code:
  200. ------------
  201. .. code-block::
  202. Package {
  203. NV Storage Block Offset //DWORD
  204. NV Storage Block Size //DWORD
  205. }
  206. .. flat-table::
  207. :widths: 1 1 2
  208. :header-rows: 1
  209. * - Field
  210. - Format
  211. - Description
  212. * - NV Storage Block Offset
  213. - DWORD
  214. - Offset in CMOS bank 0 of the verified boot non-volatile storage block, counting from
  215. the first writable CMOS byte (that is, offset=0 is the byte following the 14 bytes of
  216. clock data).
  217. * - NV Storage Block Size
  218. - DWORD
  219. - Size in bytes of the verified boot non-volatile storage block.
  220. FMAP (Chrome OS flashmap address)
  221. =================================
  222. This control method returns the physical memory address of the start of the main processor
  223. firmware flashmap.
  224. Arguments:
  225. ----------
  226. None
  227. NoneResult code:
  228. ----------------
  229. A DWORD containing the physical memory address of the start of the main processor firmware
  230. flashmap.
  231. VDTA (Chrome OS verified boot data)
  232. ===================================
  233. This control method returns the verified boot data block shared between the firmware
  234. verification step and the kernel verification step.
  235. Arguments:
  236. ----------
  237. None
  238. Result code:
  239. ------------
  240. A buffer containing the verified boot data block.
  241. MECK (Management Engine Checksum)
  242. =================================
  243. This control method returns the SHA-1 or SHA-256 hash that is read out of the Management
  244. Engine extended registers during boot. The hash is exported via ACPI so the OS can verify that
  245. the ME firmware has not changed. If Management Engine is not present, or if the firmware was
  246. unable to read the extended registers, this buffer can be zero.
  247. Arguments:
  248. ----------
  249. None
  250. Result code:
  251. ------------
  252. A buffer containing the ME hash.
  253. MLST (Chrome OS method list)
  254. ============================
  255. This control method returns a list of the other control methods supported by the Chrome OS
  256. hardware device.
  257. Arguments:
  258. ----------
  259. None
  260. Result code:
  261. ------------
  262. A package containing a list of null-terminated ASCII strings, one for each control method
  263. supported by the Chrome OS hardware device, not including the MLST method itself.
  264. For this version of the specification, the result is:
  265. .. code-block::
  266. Package {
  267. "CHSW",
  268. "FWID",
  269. "HWID",
  270. "FRID",
  271. "BINF",
  272. "GPIO",
  273. "VBNV",
  274. "FMAP",
  275. "VDTA",
  276. "MECK"
  277. }