pxa25x.c 6.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * linux/arch/arm/mach-pxa/pxa25x.c
  4. *
  5. * Author: Nicolas Pitre
  6. * Created: Jun 15, 2001
  7. * Copyright: MontaVista Software Inc.
  8. *
  9. * Code specific to PXA21x/25x/26x variants.
  10. *
  11. * Since this file should be linked before any other machine specific file,
  12. * the __initcall() here will be executed first. This serves as default
  13. * initialization stuff for PXA machines which can be overridden later if
  14. * need be.
  15. */
  16. #include <linux/dmaengine.h>
  17. #include <linux/dma/pxa-dma.h>
  18. #include <linux/gpio.h>
  19. #include <linux/gpio-pxa.h>
  20. #include <linux/module.h>
  21. #include <linux/kernel.h>
  22. #include <linux/init.h>
  23. #include <linux/platform_device.h>
  24. #include <linux/suspend.h>
  25. #include <linux/syscore_ops.h>
  26. #include <linux/irq.h>
  27. #include <linux/irqchip.h>
  28. #include <linux/platform_data/mmp_dma.h>
  29. #include <linux/soc/pxa/cpu.h>
  30. #include <linux/soc/pxa/smemc.h>
  31. #include <asm/mach/map.h>
  32. #include <asm/suspend.h>
  33. #include "irqs.h"
  34. #include "pxa25x.h"
  35. #include "reset.h"
  36. #include "pm.h"
  37. #include "addr-map.h"
  38. #include "smemc.h"
  39. #include "generic.h"
  40. #include "devices.h"
  41. /*
  42. * Various clock factors driven by the CCCR register.
  43. */
  44. #ifdef CONFIG_PM
  45. #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
  46. #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
  47. /*
  48. * List of global PXA peripheral registers to preserve.
  49. * More ones like CP and general purpose register values are preserved
  50. * with the stack pointer in sleep.S.
  51. */
  52. enum {
  53. SLEEP_SAVE_PSTR,
  54. SLEEP_SAVE_COUNT
  55. };
  56. static void pxa25x_cpu_pm_save(unsigned long *sleep_save)
  57. {
  58. SAVE(PSTR);
  59. }
  60. static void pxa25x_cpu_pm_restore(unsigned long *sleep_save)
  61. {
  62. RESTORE(PSTR);
  63. }
  64. static void pxa25x_cpu_pm_enter(suspend_state_t state)
  65. {
  66. /* Clear reset status */
  67. RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
  68. switch (state) {
  69. case PM_SUSPEND_MEM:
  70. cpu_suspend(PWRMODE_SLEEP, pxa25x_finish_suspend);
  71. break;
  72. }
  73. }
  74. static int pxa25x_cpu_pm_prepare(void)
  75. {
  76. /* set resume return address */
  77. PSPR = __pa_symbol(cpu_resume);
  78. return 0;
  79. }
  80. static void pxa25x_cpu_pm_finish(void)
  81. {
  82. /* ensure not to come back here if it wasn't intended */
  83. PSPR = 0;
  84. }
  85. static struct pxa_cpu_pm_fns pxa25x_cpu_pm_fns = {
  86. .save_count = SLEEP_SAVE_COUNT,
  87. .valid = suspend_valid_only_mem,
  88. .save = pxa25x_cpu_pm_save,
  89. .restore = pxa25x_cpu_pm_restore,
  90. .enter = pxa25x_cpu_pm_enter,
  91. .prepare = pxa25x_cpu_pm_prepare,
  92. .finish = pxa25x_cpu_pm_finish,
  93. };
  94. static void __init pxa25x_init_pm(void)
  95. {
  96. pxa_cpu_pm_fns = &pxa25x_cpu_pm_fns;
  97. }
  98. #else
  99. static inline void pxa25x_init_pm(void) {}
  100. #endif
  101. /* PXA25x: supports wakeup from GPIO0..GPIO15 and RTC alarm
  102. */
  103. static int pxa25x_set_wake(struct irq_data *d, unsigned int on)
  104. {
  105. int gpio = pxa_irq_to_gpio(d->irq);
  106. uint32_t mask = 0;
  107. if (gpio >= 0 && gpio < 85)
  108. return gpio_set_wake(gpio, on);
  109. if (d->irq == IRQ_RTCAlrm) {
  110. mask = PWER_RTC;
  111. goto set_pwer;
  112. }
  113. return -EINVAL;
  114. set_pwer:
  115. if (on)
  116. PWER |= mask;
  117. else
  118. PWER &=~mask;
  119. return 0;
  120. }
  121. void __init pxa25x_init_irq(void)
  122. {
  123. pxa_init_irq(32, pxa25x_set_wake);
  124. set_handle_irq(pxa25x_handle_irq);
  125. }
  126. static int __init __init
  127. pxa25x_dt_init_irq(struct device_node *node, struct device_node *parent)
  128. {
  129. pxa_dt_irq_init(pxa25x_set_wake);
  130. set_handle_irq(icip_handle_irq);
  131. return 0;
  132. }
  133. IRQCHIP_DECLARE(pxa25x_intc, "marvell,pxa-intc", pxa25x_dt_init_irq);
  134. static struct map_desc pxa25x_io_desc[] __initdata = {
  135. { /* Mem Ctl */
  136. .virtual = (unsigned long)SMEMC_VIRT,
  137. .pfn = __phys_to_pfn(PXA2XX_SMEMC_BASE),
  138. .length = SMEMC_SIZE,
  139. .type = MT_DEVICE
  140. }, { /* UNCACHED_PHYS_0 */
  141. .virtual = UNCACHED_PHYS_0,
  142. .pfn = __phys_to_pfn(0x00000000),
  143. .length = UNCACHED_PHYS_0_SIZE,
  144. .type = MT_DEVICE
  145. },
  146. };
  147. void __init pxa25x_map_io(void)
  148. {
  149. pxa_map_io();
  150. iotable_init(ARRAY_AND_SIZE(pxa25x_io_desc));
  151. pxa25x_get_clk_frequency_khz(1);
  152. }
  153. static struct platform_device *pxa25x_devices[] __initdata = {
  154. &pxa25x_device_gpio,
  155. &pxa25x_device_udc,
  156. &pxa_device_pmu,
  157. &pxa_device_i2s,
  158. &sa1100_device_rtc,
  159. &pxa25x_device_ssp,
  160. &pxa25x_device_nssp,
  161. &pxa25x_device_assp,
  162. &pxa25x_device_pwm0,
  163. &pxa25x_device_pwm1,
  164. &pxa_device_asoc_platform,
  165. };
  166. static const struct dma_slave_map pxa25x_slave_map[] = {
  167. /* PXA25x, PXA27x and PXA3xx common entries */
  168. { "pxa2xx-ac97", "pcm_pcm_mic_mono", PDMA_FILTER_PARAM(LOWEST, 8) },
  169. { "pxa2xx-ac97", "pcm_pcm_aux_mono_in", PDMA_FILTER_PARAM(LOWEST, 9) },
  170. { "pxa2xx-ac97", "pcm_pcm_aux_mono_out",
  171. PDMA_FILTER_PARAM(LOWEST, 10) },
  172. { "pxa2xx-ac97", "pcm_pcm_stereo_in", PDMA_FILTER_PARAM(LOWEST, 11) },
  173. { "pxa2xx-ac97", "pcm_pcm_stereo_out", PDMA_FILTER_PARAM(LOWEST, 12) },
  174. { "pxa-ssp-dai.1", "rx", PDMA_FILTER_PARAM(LOWEST, 13) },
  175. { "pxa-ssp-dai.1", "tx", PDMA_FILTER_PARAM(LOWEST, 14) },
  176. { "pxa-ssp-dai.2", "rx", PDMA_FILTER_PARAM(LOWEST, 15) },
  177. { "pxa-ssp-dai.2", "tx", PDMA_FILTER_PARAM(LOWEST, 16) },
  178. { "pxa2xx-ir", "rx", PDMA_FILTER_PARAM(LOWEST, 17) },
  179. { "pxa2xx-ir", "tx", PDMA_FILTER_PARAM(LOWEST, 18) },
  180. { "pxa2xx-mci.0", "rx", PDMA_FILTER_PARAM(LOWEST, 21) },
  181. { "pxa2xx-mci.0", "tx", PDMA_FILTER_PARAM(LOWEST, 22) },
  182. /* PXA25x specific map */
  183. { "pxa25x-ssp.0", "rx", PDMA_FILTER_PARAM(LOWEST, 13) },
  184. { "pxa25x-ssp.0", "tx", PDMA_FILTER_PARAM(LOWEST, 14) },
  185. { "pxa25x-nssp.1", "rx", PDMA_FILTER_PARAM(LOWEST, 15) },
  186. { "pxa25x-nssp.1", "tx", PDMA_FILTER_PARAM(LOWEST, 16) },
  187. { "pxa25x-nssp.2", "rx", PDMA_FILTER_PARAM(LOWEST, 23) },
  188. { "pxa25x-nssp.2", "tx", PDMA_FILTER_PARAM(LOWEST, 24) },
  189. };
  190. static struct mmp_dma_platdata pxa25x_dma_pdata = {
  191. .dma_channels = 16,
  192. .nb_requestors = 40,
  193. .slave_map = pxa25x_slave_map,
  194. .slave_map_cnt = ARRAY_SIZE(pxa25x_slave_map),
  195. };
  196. static int __init pxa25x_init(void)
  197. {
  198. int ret = 0;
  199. if (cpu_is_pxa25x()) {
  200. pxa_register_wdt(RCSR);
  201. pxa25x_init_pm();
  202. register_syscore_ops(&pxa_irq_syscore_ops);
  203. register_syscore_ops(&pxa2xx_mfp_syscore_ops);
  204. if (!of_have_populated_dt()) {
  205. software_node_register(&pxa2xx_gpiochip_node);
  206. pxa2xx_set_dmac_info(&pxa25x_dma_pdata);
  207. ret = platform_add_devices(pxa25x_devices,
  208. ARRAY_SIZE(pxa25x_devices));
  209. }
  210. }
  211. return ret;
  212. }
  213. postcore_initcall(pxa25x_init);