ls7a-pch.dtsi 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472
  1. // SPDX-License-Identifier: GPL-2.0
  2. / {
  3. pch: bus@10000000 {
  4. compatible = "simple-bus";
  5. #address-cells = <2>;
  6. #size-cells = <2>;
  7. ranges = <0 0x10000000 0 0x10000000 0 0x10000000 /* PIO & CONF & APB */
  8. 0 0x20000000 0 0x20000000 0 0x10000000
  9. 0 0x40000000 0 0x40000000 0 0x40000000 /* PCI MEM */
  10. 0xe00 0x00000000 0xe00 0x00000000 0x100 0x0000000>;
  11. pic: interrupt-controller@10000000 {
  12. compatible = "loongson,pch-pic-1.0";
  13. reg = <0 0x10000000 0 0x400>;
  14. interrupt-controller;
  15. interrupt-parent = <&htvec>;
  16. loongson,pic-base-vec = <0>;
  17. #interrupt-cells = <2>;
  18. };
  19. rtc0: rtc@100d0100 {
  20. compatible = "loongson,ls7a-rtc";
  21. reg = <0 0x100d0100 0 0x78>;
  22. interrupt-parent = <&pic>;
  23. interrupts = <52 IRQ_TYPE_LEVEL_HIGH>;
  24. };
  25. ls7a_uart0: serial@10080000 {
  26. compatible = "ns16550a";
  27. reg = <0 0x10080000 0 0x100>;
  28. clock-frequency = <50000000>;
  29. interrupt-parent = <&pic>;
  30. interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
  31. no-loopback-test;
  32. };
  33. ls7a_uart1: serial@10080100 {
  34. status = "disabled";
  35. compatible = "ns16550a";
  36. reg = <0 0x10080100 0 0x100>;
  37. clock-frequency = <50000000>;
  38. interrupt-parent = <&pic>;
  39. interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
  40. no-loopback-test;
  41. };
  42. ls7a_uart2: serial@10080200 {
  43. status = "disabled";
  44. compatible = "ns16550a";
  45. reg = <0 0x10080200 0 0x100>;
  46. clock-frequency = <50000000>;
  47. interrupt-parent = <&pic>;
  48. interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
  49. no-loopback-test;
  50. };
  51. ls7a_uart3: serial@10080300 {
  52. status = "disabled";
  53. compatible = "ns16550a";
  54. reg = <0 0x10080300 0 0x100>;
  55. clock-frequency = <50000000>;
  56. interrupt-parent = <&pic>;
  57. interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
  58. no-loopback-test;
  59. };
  60. pci@1a000000 {
  61. compatible = "loongson,ls7a-pci";
  62. device_type = "pci";
  63. #address-cells = <3>;
  64. #size-cells = <2>;
  65. msi-parent = <&msi>;
  66. reg = <0 0x1a000000 0 0x02000000>,
  67. <0xefe 0x00000000 0 0x20000000>;
  68. ranges = <0x01000000 0x0 0x00020000 0x0 0x18020000 0x0 0x00020000>,
  69. <0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>;
  70. ohci@4,0 {
  71. compatible = "pci0014,7a24.0",
  72. "pci0014,7a24",
  73. "pciclass0c0310",
  74. "pciclass0c03";
  75. reg = <0x2000 0x0 0x0 0x0 0x0>;
  76. interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
  77. interrupt-parent = <&pic>;
  78. };
  79. ehci@4,1 {
  80. compatible = "pci0014,7a14.0",
  81. "pci0014,7a14",
  82. "pciclass0c0320",
  83. "pciclass0c03";
  84. reg = <0x2100 0x0 0x0 0x0 0x0>;
  85. interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
  86. interrupt-parent = <&pic>;
  87. };
  88. ohci@5,0 {
  89. compatible = "pci0014,7a24.0",
  90. "pci0014,7a24",
  91. "pciclass0c0310",
  92. "pciclass0c03";
  93. reg = <0x2800 0x0 0x0 0x0 0x0>;
  94. interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
  95. interrupt-parent = <&pic>;
  96. };
  97. ehci@5,1 {
  98. compatible = "pci0014,7a14.0",
  99. "pci0014,7a14",
  100. "pciclass0c0320",
  101. "pciclass0c03";
  102. reg = <0x2900 0x0 0x0 0x0 0x0>;
  103. interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
  104. interrupt-parent = <&pic>;
  105. };
  106. sata@8,0 {
  107. compatible = "pci0014,7a08.0",
  108. "pci0014,7a08",
  109. "pciclass010601",
  110. "pciclass0106";
  111. reg = <0x4000 0x0 0x0 0x0 0x0>;
  112. interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
  113. interrupt-parent = <&pic>;
  114. };
  115. sata@8,1 {
  116. compatible = "pci0014,7a08.0",
  117. "pci0014,7a08",
  118. "pciclass010601",
  119. "pciclass0106";
  120. reg = <0x4100 0x0 0x0 0x0 0x0>;
  121. interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
  122. interrupt-parent = <&pic>;
  123. };
  124. sata@8,2 {
  125. compatible = "pci0014,7a08.0",
  126. "pci0014,7a08",
  127. "pciclass010601",
  128. "pciclass0106";
  129. reg = <0x4200 0x0 0x0 0x0 0x0>;
  130. interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
  131. interrupt-parent = <&pic>;
  132. };
  133. gpu@6,0 {
  134. compatible = "pci0014,7a15.0",
  135. "pci0014,7a15",
  136. "pciclass030200",
  137. "pciclass0302";
  138. reg = <0x3000 0x0 0x0 0x0 0x0>;
  139. interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;
  140. interrupt-parent = <&pic>;
  141. };
  142. dc@6,1 {
  143. compatible = "pci0014,7a06.0",
  144. "pci0014,7a06",
  145. "pciclass030000",
  146. "pciclass0300";
  147. reg = <0x3100 0x0 0x0 0x0 0x0>;
  148. interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
  149. interrupt-parent = <&pic>;
  150. };
  151. hda@7,0 {
  152. compatible = "pci0014,7a07.0",
  153. "pci0014,7a07",
  154. "pciclass040300",
  155. "pciclass0403";
  156. reg = <0x3800 0x0 0x0 0x0 0x0>;
  157. interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
  158. interrupt-parent = <&pic>;
  159. };
  160. gmac@3,0 {
  161. compatible = "pci0014,7a03.0",
  162. "pci0014,7a03",
  163. "pciclass020000",
  164. "pciclass0200";
  165. reg = <0x1800 0x0 0x0 0x0 0x0>;
  166. interrupts = <12 IRQ_TYPE_LEVEL_HIGH>,
  167. <13 IRQ_TYPE_LEVEL_HIGH>;
  168. interrupt-names = "macirq", "eth_lpi";
  169. interrupt-parent = <&pic>;
  170. phy-mode = "rgmii";
  171. mdio {
  172. #address-cells = <1>;
  173. #size-cells = <0>;
  174. compatible = "snps,dwmac-mdio";
  175. phy0: ethernet-phy@0 {
  176. reg = <0>;
  177. };
  178. };
  179. };
  180. gmac@3,1 {
  181. compatible = "pci0014,7a03.0",
  182. "pci0014,7a03",
  183. "pciclass020000",
  184. "pciclass0200",
  185. "loongson, pci-gmac";
  186. reg = <0x1900 0x0 0x0 0x0 0x0>;
  187. interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
  188. <15 IRQ_TYPE_LEVEL_HIGH>;
  189. interrupt-names = "macirq", "eth_lpi";
  190. interrupt-parent = <&pic>;
  191. phy-mode = "rgmii";
  192. mdio {
  193. #address-cells = <1>;
  194. #size-cells = <0>;
  195. compatible = "snps,dwmac-mdio";
  196. phy1: ethernet-phy@1 {
  197. reg = <0>;
  198. };
  199. };
  200. };
  201. pcie@9,0 {
  202. compatible = "pci0014,7a19.1",
  203. "pci0014,7a19",
  204. "pciclass060400",
  205. "pciclass0604";
  206. reg = <0x4800 0x0 0x0 0x0 0x0>;
  207. interrupts = <32 IRQ_TYPE_LEVEL_HIGH>;
  208. interrupt-parent = <&pic>;
  209. #address-cells = <3>;
  210. #size-cells = <2>;
  211. device_type = "pci";
  212. #interrupt-cells = <1>;
  213. interrupt-map-mask = <0 0 0 0>;
  214. interrupt-map = <0 0 0 0 &pic 32 IRQ_TYPE_LEVEL_HIGH>;
  215. ranges;
  216. };
  217. pcie@a,0 {
  218. compatible = "pci0014,7a09.1",
  219. "pci0014,7a09",
  220. "pciclass060400",
  221. "pciclass0604";
  222. reg = <0x5000 0x0 0x0 0x0 0x0>;
  223. interrupts = <33 IRQ_TYPE_LEVEL_HIGH>;
  224. interrupt-parent = <&pic>;
  225. #address-cells = <3>;
  226. #size-cells = <2>;
  227. device_type = "pci";
  228. #interrupt-cells = <1>;
  229. interrupt-map-mask = <0 0 0 0>;
  230. interrupt-map = <0 0 0 0 &pic 33 IRQ_TYPE_LEVEL_HIGH>;
  231. ranges;
  232. };
  233. pcie@b,0 {
  234. compatible = "pci0014,7a09.1",
  235. "pci0014,7a09",
  236. "pciclass060400",
  237. "pciclass0604";
  238. reg = <0x5800 0x0 0x0 0x0 0x0>;
  239. interrupts = <34 IRQ_TYPE_LEVEL_HIGH>;
  240. interrupt-parent = <&pic>;
  241. #address-cells = <3>;
  242. #size-cells = <2>;
  243. device_type = "pci";
  244. #interrupt-cells = <1>;
  245. interrupt-map-mask = <0 0 0 0>;
  246. interrupt-map = <0 0 0 0 &pic 34 IRQ_TYPE_LEVEL_HIGH>;
  247. ranges;
  248. };
  249. pcie@c,0 {
  250. compatible = "pci0014,7a09.1",
  251. "pci0014,7a09",
  252. "pciclass060400",
  253. "pciclass0604";
  254. reg = <0x6000 0x0 0x0 0x0 0x0>;
  255. interrupts = <35 IRQ_TYPE_LEVEL_HIGH>;
  256. interrupt-parent = <&pic>;
  257. #address-cells = <3>;
  258. #size-cells = <2>;
  259. device_type = "pci";
  260. #interrupt-cells = <1>;
  261. interrupt-map-mask = <0 0 0 0>;
  262. interrupt-map = <0 0 0 0 &pic 35 IRQ_TYPE_LEVEL_HIGH>;
  263. ranges;
  264. };
  265. pcie@d,0 {
  266. compatible = "pci0014,7a19.1",
  267. "pci0014,7a19",
  268. "pciclass060400",
  269. "pciclass0604";
  270. reg = <0x6800 0x0 0x0 0x0 0x0>;
  271. interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
  272. interrupt-parent = <&pic>;
  273. #address-cells = <3>;
  274. #size-cells = <2>;
  275. device_type = "pci";
  276. #interrupt-cells = <1>;
  277. interrupt-map-mask = <0 0 0 0>;
  278. interrupt-map = <0 0 0 0 &pic 36 IRQ_TYPE_LEVEL_HIGH>;
  279. ranges;
  280. };
  281. pcie@e,0 {
  282. compatible = "pci0014,7a09.1",
  283. "pci0014,7a09",
  284. "pciclass060400",
  285. "pciclass0604";
  286. reg = <0x7000 0x0 0x0 0x0 0x0>;
  287. interrupts = <37 IRQ_TYPE_LEVEL_HIGH>;
  288. interrupt-parent = <&pic>;
  289. #address-cells = <3>;
  290. #size-cells = <2>;
  291. device_type = "pci";
  292. #interrupt-cells = <1>;
  293. interrupt-map-mask = <0 0 0 0>;
  294. interrupt-map = <0 0 0 0 &pic 37 IRQ_TYPE_LEVEL_HIGH>;
  295. ranges;
  296. };
  297. pcie@f,0 {
  298. compatible = "pci0014,7a29.1",
  299. "pci0014,7a29",
  300. "pciclass060400",
  301. "pciclass0604";
  302. reg = <0x7800 0x0 0x0 0x0 0x0>;
  303. interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;
  304. interrupt-parent = <&pic>;
  305. #address-cells = <3>;
  306. #size-cells = <2>;
  307. device_type = "pci";
  308. #interrupt-cells = <1>;
  309. interrupt-map-mask = <0 0 0 0>;
  310. interrupt-map = <0 0 0 0 &pic 40 IRQ_TYPE_LEVEL_HIGH>;
  311. ranges;
  312. };
  313. pcie@10,0 {
  314. compatible = "pci0014,7a19.1",
  315. "pci0014,7a19",
  316. "pciclass060400",
  317. "pciclass0604";
  318. reg = <0x8000 0x0 0x0 0x0 0x0>;
  319. interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
  320. interrupt-parent = <&pic>;
  321. #address-cells = <3>;
  322. #size-cells = <2>;
  323. device_type = "pci";
  324. #interrupt-cells = <1>;
  325. interrupt-map-mask = <0 0 0 0>;
  326. interrupt-map = <0 0 0 0 &pic 41 IRQ_TYPE_LEVEL_HIGH>;
  327. ranges;
  328. };
  329. pcie@11,0 {
  330. compatible = "pci0014,7a29.1",
  331. "pci0014,7a29",
  332. "pciclass060400",
  333. "pciclass0604";
  334. reg = <0x8800 0x0 0x0 0x0 0x0>;
  335. interrupts = <42 IRQ_TYPE_LEVEL_HIGH>;
  336. interrupt-parent = <&pic>;
  337. #address-cells = <3>;
  338. #size-cells = <2>;
  339. device_type = "pci";
  340. #interrupt-cells = <1>;
  341. interrupt-map-mask = <0 0 0 0>;
  342. interrupt-map = <0 0 0 0 &pic 42 IRQ_TYPE_LEVEL_HIGH>;
  343. ranges;
  344. };
  345. pcie@12,0 {
  346. compatible = "pci0014,7a19.1",
  347. "pci0014,7a19",
  348. "pciclass060400",
  349. "pciclass0604";
  350. reg = <0x9000 0x0 0x0 0x0 0x0>;
  351. interrupts = <43 IRQ_TYPE_LEVEL_HIGH>;
  352. interrupt-parent = <&pic>;
  353. #address-cells = <3>;
  354. #size-cells = <2>;
  355. device_type = "pci";
  356. #interrupt-cells = <1>;
  357. interrupt-map-mask = <0 0 0 0>;
  358. interrupt-map = <0 0 0 0 &pic 43 IRQ_TYPE_LEVEL_HIGH>;
  359. ranges;
  360. };
  361. pcie@13,0 {
  362. compatible = "pci0014,7a29.1",
  363. "pci0014,7a29",
  364. "pciclass060400",
  365. "pciclass0604";
  366. reg = <0x9800 0x0 0x0 0x0 0x0>;
  367. interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
  368. interrupt-parent = <&pic>;
  369. #address-cells = <3>;
  370. #size-cells = <2>;
  371. device_type = "pci";
  372. #interrupt-cells = <1>;
  373. interrupt-map-mask = <0 0 0 0>;
  374. interrupt-map = <0 0 0 0 &pic 38 IRQ_TYPE_LEVEL_HIGH>;
  375. ranges;
  376. };
  377. pcie@14,0 {
  378. compatible = "pci0014,7a19.1",
  379. "pci0014,7a19",
  380. "pciclass060400",
  381. "pciclass0604";
  382. reg = <0xa000 0x0 0x0 0x0 0x0>;
  383. interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
  384. interrupt-parent = <&pic>;
  385. #address-cells = <3>;
  386. #size-cells = <2>;
  387. device_type = "pci";
  388. #interrupt-cells = <1>;
  389. interrupt-map-mask = <0 0 0 0>;
  390. interrupt-map = <0 0 0 0 &pic 39 IRQ_TYPE_LEVEL_HIGH>;
  391. ranges;
  392. };
  393. };
  394. isa@18000000 {
  395. compatible = "isa";
  396. #address-cells = <2>;
  397. #size-cells = <1>;
  398. ranges = <1 0 0 0x18000000 0x20000>;
  399. };
  400. };
  401. };