processor_32.h 4.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * include/asm-sh/processor.h
  4. *
  5. * Copyright (C) 1999, 2000 Niibe Yutaka
  6. * Copyright (C) 2002, 2003 Paul Mundt
  7. */
  8. #ifndef __ASM_SH_PROCESSOR_32_H
  9. #define __ASM_SH_PROCESSOR_32_H
  10. #include <linux/compiler.h>
  11. #include <linux/linkage.h>
  12. #include <asm/page.h>
  13. #include <asm/types.h>
  14. #include <asm/hw_breakpoint.h>
  15. /* Core Processor Version Register */
  16. #define CCN_PVR 0xff000030
  17. #define CCN_CVR 0xff000040
  18. #define CCN_PRR 0xff000044
  19. /*
  20. * User space process size: 2GB.
  21. *
  22. * Since SH7709 and SH7750 have "area 7", we can't use 0x7c000000--0x7fffffff
  23. */
  24. #define TASK_SIZE 0x7c000000UL
  25. #define STACK_TOP TASK_SIZE
  26. #define STACK_TOP_MAX STACK_TOP
  27. /* This decides where the kernel will search for a free chunk of vm
  28. * space during mmap's.
  29. */
  30. #define TASK_UNMAPPED_BASE PAGE_ALIGN(TASK_SIZE / 3)
  31. /*
  32. * Bit of SR register
  33. *
  34. * FD-bit:
  35. * When it's set, it means the processor doesn't have right to use FPU,
  36. * and it results exception when the floating operation is executed.
  37. *
  38. * IMASK-bit:
  39. * Interrupt level mask
  40. */
  41. #define SR_DSP 0x00001000
  42. #define SR_IMASK 0x000000f0
  43. #define SR_FD 0x00008000
  44. #define SR_MD 0x40000000
  45. #define SR_USER_MASK 0x00000303 // M, Q, S, T bits
  46. /*
  47. * DSP structure and data
  48. */
  49. struct sh_dsp_struct {
  50. unsigned long dsp_regs[14];
  51. long status;
  52. };
  53. /*
  54. * FPU structure and data
  55. */
  56. struct sh_fpu_hard_struct {
  57. unsigned long fp_regs[16];
  58. unsigned long xfp_regs[16];
  59. unsigned long fpscr;
  60. unsigned long fpul;
  61. long status; /* software status information */
  62. };
  63. /* Dummy fpu emulator */
  64. struct sh_fpu_soft_struct {
  65. unsigned long fp_regs[16];
  66. unsigned long xfp_regs[16];
  67. unsigned long fpscr;
  68. unsigned long fpul;
  69. unsigned char lookahead;
  70. unsigned long entry_pc;
  71. };
  72. union thread_xstate {
  73. struct sh_fpu_hard_struct hardfpu;
  74. struct sh_fpu_soft_struct softfpu;
  75. };
  76. struct thread_struct {
  77. /* Saved registers when thread is descheduled */
  78. unsigned long sp;
  79. unsigned long pc;
  80. /* Various thread flags, see SH_THREAD_xxx */
  81. unsigned long flags;
  82. /* Save middle states of ptrace breakpoints */
  83. struct perf_event *ptrace_bps[HBP_NUM];
  84. #ifdef CONFIG_SH_DSP
  85. /* Dsp status information */
  86. struct sh_dsp_struct dsp_status;
  87. #endif
  88. /* Extended processor state */
  89. union thread_xstate *xstate;
  90. /*
  91. * fpu_counter contains the number of consecutive context switches
  92. * that the FPU is used. If this is over a threshold, the lazy fpu
  93. * saving becomes unlazy to save the trap. This is an unsigned char
  94. * so that after 256 times the counter wraps and the behavior turns
  95. * lazy again; this to deal with bursty apps that only use FPU for
  96. * a short time
  97. */
  98. unsigned char fpu_counter;
  99. };
  100. #define INIT_THREAD { \
  101. .sp = sizeof(init_stack) + (long) &init_stack, \
  102. .flags = 0, \
  103. }
  104. /* Forward declaration, a strange C thing */
  105. struct task_struct;
  106. extern void start_thread(struct pt_regs *regs, unsigned long new_pc, unsigned long new_sp);
  107. /*
  108. * FPU lazy state save handling.
  109. */
  110. static __inline__ void disable_fpu(void)
  111. {
  112. unsigned long __dummy;
  113. /* Set FD flag in SR */
  114. __asm__ __volatile__("stc sr, %0\n\t"
  115. "or %1, %0\n\t"
  116. "ldc %0, sr"
  117. : "=&r" (__dummy)
  118. : "r" (SR_FD));
  119. }
  120. static __inline__ void enable_fpu(void)
  121. {
  122. unsigned long __dummy;
  123. /* Clear out FD flag in SR */
  124. __asm__ __volatile__("stc sr, %0\n\t"
  125. "and %1, %0\n\t"
  126. "ldc %0, sr"
  127. : "=&r" (__dummy)
  128. : "r" (~SR_FD));
  129. }
  130. /* Double presision, NANS as NANS, rounding to nearest, no exceptions */
  131. #define FPSCR_INIT 0x00080000
  132. #define FPSCR_CAUSE_MASK 0x0001f000 /* Cause bits */
  133. #define FPSCR_FLAG_MASK 0x0000007c /* Flag bits */
  134. /*
  135. * Return saved PC of a blocked thread.
  136. */
  137. #define thread_saved_pc(tsk) (tsk->thread.pc)
  138. void show_trace(struct task_struct *tsk, unsigned long *sp,
  139. struct pt_regs *regs, const char *loglvl);
  140. #ifdef CONFIG_DUMP_CODE
  141. void show_code(struct pt_regs *regs);
  142. #else
  143. static inline void show_code(struct pt_regs *regs)
  144. {
  145. }
  146. #endif
  147. extern unsigned long __get_wchan(struct task_struct *p);
  148. #define KSTK_EIP(tsk) (task_pt_regs(tsk)->pc)
  149. #define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[15])
  150. #if defined(CONFIG_CPU_SH2A) || defined(CONFIG_CPU_SH4)
  151. #define PREFETCH_STRIDE L1_CACHE_BYTES
  152. #define ARCH_HAS_PREFETCH
  153. #define ARCH_HAS_PREFETCHW
  154. static inline void prefetch(const void *x)
  155. {
  156. __builtin_prefetch(x, 0, 3);
  157. }
  158. static inline void prefetchw(const void *x)
  159. {
  160. __builtin_prefetch(x, 1, 3);
  161. }
  162. #endif
  163. #endif /* __ASM_SH_PROCESSOR_32_H */