extcon-intel-cht-wc.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Extcon charger detection driver for Intel Cherrytrail Whiskey Cove PMIC
  4. * Copyright (C) 2017 Hans de Goede <hdegoede@redhat.com>
  5. *
  6. * Based on various non upstream patches to support the CHT Whiskey Cove PMIC:
  7. * Copyright (C) 2013-2015 Intel Corporation. All rights reserved.
  8. */
  9. #include <linux/extcon-provider.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/kernel.h>
  12. #include <linux/mfd/intel_soc_pmic.h>
  13. #include <linux/module.h>
  14. #include <linux/mod_devicetable.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/power_supply.h>
  17. #include <linux/property.h>
  18. #include <linux/regmap.h>
  19. #include <linux/regulator/consumer.h>
  20. #include <linux/slab.h>
  21. #include <linux/usb/role.h>
  22. #include "extcon-intel.h"
  23. #define CHT_WC_PHYCTRL 0x5e07
  24. #define CHT_WC_CHGRCTRL0 0x5e16
  25. #define CHT_WC_CHGRCTRL0_CHGRRESET BIT(0)
  26. #define CHT_WC_CHGRCTRL0_EMRGCHREN BIT(1)
  27. #define CHT_WC_CHGRCTRL0_EXTCHRDIS BIT(2)
  28. #define CHT_WC_CHGRCTRL0_SWCONTROL BIT(3)
  29. #define CHT_WC_CHGRCTRL0_TTLCK BIT(4)
  30. #define CHT_WC_CHGRCTRL0_CCSM_OFF BIT(5)
  31. #define CHT_WC_CHGRCTRL0_DBPOFF BIT(6)
  32. #define CHT_WC_CHGRCTRL0_CHR_WDT_NOKICK BIT(7)
  33. #define CHT_WC_CHGRCTRL1 0x5e17
  34. #define CHT_WC_CHGRCTRL1_FUSB_INLMT_100 BIT(0)
  35. #define CHT_WC_CHGRCTRL1_FUSB_INLMT_150 BIT(1)
  36. #define CHT_WC_CHGRCTRL1_FUSB_INLMT_500 BIT(2)
  37. #define CHT_WC_CHGRCTRL1_FUSB_INLMT_900 BIT(3)
  38. #define CHT_WC_CHGRCTRL1_FUSB_INLMT_1500 BIT(4)
  39. #define CHT_WC_CHGRCTRL1_FTEMP_EVENT BIT(5)
  40. #define CHT_WC_CHGRCTRL1_OTGMODE BIT(6)
  41. #define CHT_WC_CHGRCTRL1_DBPEN BIT(7)
  42. #define CHT_WC_USBSRC 0x5e29
  43. #define CHT_WC_USBSRC_STS_MASK GENMASK(1, 0)
  44. #define CHT_WC_USBSRC_STS_SUCCESS 2
  45. #define CHT_WC_USBSRC_STS_FAIL 3
  46. #define CHT_WC_USBSRC_TYPE_SHIFT 2
  47. #define CHT_WC_USBSRC_TYPE_MASK GENMASK(5, 2)
  48. #define CHT_WC_USBSRC_TYPE_NONE 0
  49. #define CHT_WC_USBSRC_TYPE_SDP 1
  50. #define CHT_WC_USBSRC_TYPE_DCP 2
  51. #define CHT_WC_USBSRC_TYPE_CDP 3
  52. #define CHT_WC_USBSRC_TYPE_ACA 4
  53. #define CHT_WC_USBSRC_TYPE_SE1 5
  54. #define CHT_WC_USBSRC_TYPE_MHL 6
  55. #define CHT_WC_USBSRC_TYPE_FLOATING 7
  56. #define CHT_WC_USBSRC_TYPE_OTHER 8
  57. #define CHT_WC_USBSRC_TYPE_DCP_EXTPHY 9
  58. #define CHT_WC_CHGDISCTRL 0x5e2f
  59. #define CHT_WC_CHGDISCTRL_OUT BIT(0)
  60. /* 0 - open drain, 1 - regular push-pull output */
  61. #define CHT_WC_CHGDISCTRL_DRV BIT(4)
  62. /* 0 - pin is controlled by SW, 1 - by HW */
  63. #define CHT_WC_CHGDISCTRL_FN BIT(6)
  64. #define CHT_WC_PWRSRC_IRQ 0x6e03
  65. #define CHT_WC_PWRSRC_IRQ_MASK 0x6e0f
  66. #define CHT_WC_PWRSRC_STS 0x6e1e
  67. #define CHT_WC_PWRSRC_VBUS BIT(0)
  68. #define CHT_WC_PWRSRC_DC BIT(1)
  69. #define CHT_WC_PWRSRC_BATT BIT(2)
  70. #define CHT_WC_PWRSRC_USBID_MASK GENMASK(4, 3)
  71. #define CHT_WC_PWRSRC_USBID_SHIFT 3
  72. #define CHT_WC_PWRSRC_RID_ACA 0
  73. #define CHT_WC_PWRSRC_RID_GND 1
  74. #define CHT_WC_PWRSRC_RID_FLOAT 2
  75. #define CHT_WC_VBUS_GPIO_CTLO 0x6e2d
  76. #define CHT_WC_VBUS_GPIO_CTLO_OUTPUT BIT(0)
  77. #define CHT_WC_VBUS_GPIO_CTLO_DRV_OD BIT(4)
  78. #define CHT_WC_VBUS_GPIO_CTLO_DIR_OUT BIT(5)
  79. enum cht_wc_mux_select {
  80. MUX_SEL_PMIC = 0,
  81. MUX_SEL_SOC,
  82. };
  83. static const unsigned int cht_wc_extcon_cables[] = {
  84. EXTCON_USB,
  85. EXTCON_USB_HOST,
  86. EXTCON_CHG_USB_SDP,
  87. EXTCON_CHG_USB_CDP,
  88. EXTCON_CHG_USB_DCP,
  89. EXTCON_CHG_USB_ACA,
  90. EXTCON_NONE,
  91. };
  92. struct cht_wc_extcon_data {
  93. struct device *dev;
  94. struct regmap *regmap;
  95. struct extcon_dev *edev;
  96. struct usb_role_switch *role_sw;
  97. struct regulator *vbus_boost;
  98. struct power_supply *psy;
  99. enum power_supply_usb_type usb_type;
  100. unsigned int previous_cable;
  101. bool usb_host;
  102. bool vbus_boost_enabled;
  103. };
  104. static int cht_wc_extcon_get_id(struct cht_wc_extcon_data *ext, int pwrsrc_sts)
  105. {
  106. switch ((pwrsrc_sts & CHT_WC_PWRSRC_USBID_MASK) >> CHT_WC_PWRSRC_USBID_SHIFT) {
  107. case CHT_WC_PWRSRC_RID_GND:
  108. return INTEL_USB_ID_GND;
  109. case CHT_WC_PWRSRC_RID_FLOAT:
  110. return INTEL_USB_ID_FLOAT;
  111. /*
  112. * According to the spec. we should read the USB-ID pin ADC value here
  113. * to determine the resistance of the used pull-down resister and then
  114. * return RID_A / RID_B / RID_C based on this. But all "Accessory
  115. * Charger Adapter"s (ACAs) which users can actually buy always use
  116. * a combination of a charging port with one or more USB-A ports, so
  117. * they should always use a resistor indicating RID_A. But the spec
  118. * is hard to read / badly-worded so some of them actually indicate
  119. * they are a RID_B ACA evnen though they clearly are a RID_A ACA.
  120. * To workaround this simply always return INTEL_USB_RID_A, which
  121. * matches all the ACAs which users can actually buy.
  122. */
  123. case CHT_WC_PWRSRC_RID_ACA:
  124. return INTEL_USB_RID_A;
  125. default:
  126. return INTEL_USB_ID_FLOAT;
  127. }
  128. }
  129. static int cht_wc_extcon_get_charger(struct cht_wc_extcon_data *ext,
  130. bool ignore_errors)
  131. {
  132. int ret, usbsrc, status;
  133. unsigned long timeout;
  134. /* Charger detection can take upto 600ms, wait 800ms max. */
  135. timeout = jiffies + msecs_to_jiffies(800);
  136. do {
  137. ret = regmap_read(ext->regmap, CHT_WC_USBSRC, &usbsrc);
  138. if (ret) {
  139. dev_err(ext->dev, "Error reading usbsrc: %d\n", ret);
  140. return ret;
  141. }
  142. status = usbsrc & CHT_WC_USBSRC_STS_MASK;
  143. if (status == CHT_WC_USBSRC_STS_SUCCESS ||
  144. status == CHT_WC_USBSRC_STS_FAIL)
  145. break;
  146. msleep(50); /* Wait a bit before retrying */
  147. } while (time_before(jiffies, timeout));
  148. if (status != CHT_WC_USBSRC_STS_SUCCESS) {
  149. if (!ignore_errors) {
  150. if (status == CHT_WC_USBSRC_STS_FAIL)
  151. dev_warn(ext->dev, "Could not detect charger type\n");
  152. else
  153. dev_warn(ext->dev, "Timeout detecting charger type\n");
  154. }
  155. /* Safe fallback */
  156. usbsrc = CHT_WC_USBSRC_TYPE_SDP << CHT_WC_USBSRC_TYPE_SHIFT;
  157. }
  158. usbsrc = (usbsrc & CHT_WC_USBSRC_TYPE_MASK) >> CHT_WC_USBSRC_TYPE_SHIFT;
  159. switch (usbsrc) {
  160. default:
  161. dev_warn(ext->dev,
  162. "Unhandled charger type %d, defaulting to SDP\n",
  163. ret);
  164. ext->usb_type = POWER_SUPPLY_USB_TYPE_SDP;
  165. return EXTCON_CHG_USB_SDP;
  166. case CHT_WC_USBSRC_TYPE_SDP:
  167. case CHT_WC_USBSRC_TYPE_FLOATING:
  168. case CHT_WC_USBSRC_TYPE_OTHER:
  169. ext->usb_type = POWER_SUPPLY_USB_TYPE_SDP;
  170. return EXTCON_CHG_USB_SDP;
  171. case CHT_WC_USBSRC_TYPE_CDP:
  172. ext->usb_type = POWER_SUPPLY_USB_TYPE_CDP;
  173. return EXTCON_CHG_USB_CDP;
  174. case CHT_WC_USBSRC_TYPE_DCP:
  175. case CHT_WC_USBSRC_TYPE_DCP_EXTPHY:
  176. case CHT_WC_USBSRC_TYPE_MHL: /* MHL2+ delivers upto 2A, treat as DCP */
  177. ext->usb_type = POWER_SUPPLY_USB_TYPE_DCP;
  178. return EXTCON_CHG_USB_DCP;
  179. case CHT_WC_USBSRC_TYPE_ACA:
  180. ext->usb_type = POWER_SUPPLY_USB_TYPE_ACA;
  181. return EXTCON_CHG_USB_ACA;
  182. }
  183. }
  184. static void cht_wc_extcon_set_phymux(struct cht_wc_extcon_data *ext, u8 state)
  185. {
  186. int ret;
  187. ret = regmap_write(ext->regmap, CHT_WC_PHYCTRL, state);
  188. if (ret)
  189. dev_err(ext->dev, "Error writing phyctrl: %d\n", ret);
  190. }
  191. static void cht_wc_extcon_set_5v_boost(struct cht_wc_extcon_data *ext,
  192. bool enable)
  193. {
  194. int ret, val;
  195. /*
  196. * The 5V boost converter is enabled through a gpio on the PMIC, since
  197. * there currently is no gpio driver we access the gpio reg directly.
  198. */
  199. val = CHT_WC_VBUS_GPIO_CTLO_DRV_OD | CHT_WC_VBUS_GPIO_CTLO_DIR_OUT;
  200. if (enable)
  201. val |= CHT_WC_VBUS_GPIO_CTLO_OUTPUT;
  202. ret = regmap_write(ext->regmap, CHT_WC_VBUS_GPIO_CTLO, val);
  203. if (ret)
  204. dev_err(ext->dev, "Error writing Vbus GPIO CTLO: %d\n", ret);
  205. }
  206. static void cht_wc_extcon_set_otgmode(struct cht_wc_extcon_data *ext,
  207. bool enable)
  208. {
  209. unsigned int val = enable ? CHT_WC_CHGRCTRL1_OTGMODE : 0;
  210. int ret;
  211. ret = regmap_update_bits(ext->regmap, CHT_WC_CHGRCTRL1,
  212. CHT_WC_CHGRCTRL1_OTGMODE, val);
  213. if (ret)
  214. dev_err(ext->dev, "Error updating CHGRCTRL1 reg: %d\n", ret);
  215. if (ext->vbus_boost && ext->vbus_boost_enabled != enable) {
  216. if (enable)
  217. ret = regulator_enable(ext->vbus_boost);
  218. else
  219. ret = regulator_disable(ext->vbus_boost);
  220. if (ret)
  221. dev_err(ext->dev, "Error updating Vbus boost regulator: %d\n", ret);
  222. else
  223. ext->vbus_boost_enabled = enable;
  224. }
  225. }
  226. static void cht_wc_extcon_enable_charging(struct cht_wc_extcon_data *ext,
  227. bool enable)
  228. {
  229. unsigned int val = enable ? 0 : CHT_WC_CHGDISCTRL_OUT;
  230. int ret;
  231. ret = regmap_update_bits(ext->regmap, CHT_WC_CHGDISCTRL,
  232. CHT_WC_CHGDISCTRL_OUT, val);
  233. if (ret)
  234. dev_err(ext->dev, "Error updating CHGDISCTRL reg: %d\n", ret);
  235. }
  236. /* Small helper to sync EXTCON_CHG_USB_SDP and EXTCON_USB state */
  237. static void cht_wc_extcon_set_state(struct cht_wc_extcon_data *ext,
  238. unsigned int cable, bool state)
  239. {
  240. extcon_set_state_sync(ext->edev, cable, state);
  241. if (cable == EXTCON_CHG_USB_SDP)
  242. extcon_set_state_sync(ext->edev, EXTCON_USB, state);
  243. }
  244. static void cht_wc_extcon_pwrsrc_event(struct cht_wc_extcon_data *ext)
  245. {
  246. int ret, pwrsrc_sts, id;
  247. unsigned int cable = EXTCON_NONE;
  248. /* Ignore errors in host mode, as the 5v boost converter is on then */
  249. bool ignore_get_charger_errors = ext->usb_host;
  250. enum usb_role role;
  251. ext->usb_type = POWER_SUPPLY_USB_TYPE_UNKNOWN;
  252. ret = regmap_read(ext->regmap, CHT_WC_PWRSRC_STS, &pwrsrc_sts);
  253. if (ret) {
  254. dev_err(ext->dev, "Error reading pwrsrc status: %d\n", ret);
  255. return;
  256. }
  257. id = cht_wc_extcon_get_id(ext, pwrsrc_sts);
  258. if (id == INTEL_USB_ID_GND) {
  259. cht_wc_extcon_enable_charging(ext, false);
  260. cht_wc_extcon_set_otgmode(ext, true);
  261. /* The 5v boost causes a false VBUS / SDP detect, skip */
  262. goto charger_det_done;
  263. }
  264. cht_wc_extcon_set_otgmode(ext, false);
  265. cht_wc_extcon_enable_charging(ext, true);
  266. /* Plugged into a host/charger or not connected? */
  267. if (!(pwrsrc_sts & CHT_WC_PWRSRC_VBUS)) {
  268. /* Route D+ and D- to PMIC for future charger detection */
  269. cht_wc_extcon_set_phymux(ext, MUX_SEL_PMIC);
  270. goto set_state;
  271. }
  272. ret = cht_wc_extcon_get_charger(ext, ignore_get_charger_errors);
  273. if (ret >= 0)
  274. cable = ret;
  275. charger_det_done:
  276. /* Route D+ and D- to SoC for the host or gadget controller */
  277. cht_wc_extcon_set_phymux(ext, MUX_SEL_SOC);
  278. set_state:
  279. if (cable != ext->previous_cable) {
  280. cht_wc_extcon_set_state(ext, cable, true);
  281. cht_wc_extcon_set_state(ext, ext->previous_cable, false);
  282. ext->previous_cable = cable;
  283. }
  284. ext->usb_host = ((id == INTEL_USB_ID_GND) || (id == INTEL_USB_RID_A));
  285. extcon_set_state_sync(ext->edev, EXTCON_USB_HOST, ext->usb_host);
  286. if (ext->usb_host)
  287. role = USB_ROLE_HOST;
  288. else if (pwrsrc_sts & CHT_WC_PWRSRC_VBUS)
  289. role = USB_ROLE_DEVICE;
  290. else
  291. role = USB_ROLE_NONE;
  292. /* Note: this is a no-op when ext->role_sw is NULL */
  293. ret = usb_role_switch_set_role(ext->role_sw, role);
  294. if (ret)
  295. dev_err(ext->dev, "Error setting USB-role: %d\n", ret);
  296. if (ext->psy)
  297. power_supply_changed(ext->psy);
  298. }
  299. static irqreturn_t cht_wc_extcon_isr(int irq, void *data)
  300. {
  301. struct cht_wc_extcon_data *ext = data;
  302. int ret, irqs;
  303. ret = regmap_read(ext->regmap, CHT_WC_PWRSRC_IRQ, &irqs);
  304. if (ret) {
  305. dev_err(ext->dev, "Error reading irqs: %d\n", ret);
  306. return IRQ_NONE;
  307. }
  308. cht_wc_extcon_pwrsrc_event(ext);
  309. ret = regmap_write(ext->regmap, CHT_WC_PWRSRC_IRQ, irqs);
  310. if (ret) {
  311. dev_err(ext->dev, "Error writing irqs: %d\n", ret);
  312. return IRQ_NONE;
  313. }
  314. return IRQ_HANDLED;
  315. }
  316. static int cht_wc_extcon_sw_control(struct cht_wc_extcon_data *ext, bool enable)
  317. {
  318. int ret, mask, val;
  319. val = enable ? 0 : CHT_WC_CHGDISCTRL_FN;
  320. ret = regmap_update_bits(ext->regmap, CHT_WC_CHGDISCTRL,
  321. CHT_WC_CHGDISCTRL_FN, val);
  322. if (ret)
  323. dev_err(ext->dev,
  324. "Error setting sw control for CHGDIS pin: %d\n",
  325. ret);
  326. mask = CHT_WC_CHGRCTRL0_SWCONTROL | CHT_WC_CHGRCTRL0_CCSM_OFF;
  327. val = enable ? mask : 0;
  328. ret = regmap_update_bits(ext->regmap, CHT_WC_CHGRCTRL0, mask, val);
  329. if (ret)
  330. dev_err(ext->dev, "Error setting sw control: %d\n", ret);
  331. return ret;
  332. }
  333. static int cht_wc_extcon_find_role_sw(struct cht_wc_extcon_data *ext)
  334. {
  335. const struct software_node *swnode;
  336. struct fwnode_handle *fwnode;
  337. swnode = software_node_find_by_name(NULL, "intel-xhci-usb-sw");
  338. if (!swnode)
  339. return -EPROBE_DEFER;
  340. fwnode = software_node_fwnode(swnode);
  341. ext->role_sw = usb_role_switch_find_by_fwnode(fwnode);
  342. fwnode_handle_put(fwnode);
  343. return ext->role_sw ? 0 : -EPROBE_DEFER;
  344. }
  345. static void cht_wc_extcon_put_role_sw(void *data)
  346. {
  347. struct cht_wc_extcon_data *ext = data;
  348. usb_role_switch_put(ext->role_sw);
  349. }
  350. /* Some boards require controlling the role-sw and Vbus based on the id-pin */
  351. static int cht_wc_extcon_get_role_sw_and_regulator(struct cht_wc_extcon_data *ext)
  352. {
  353. int ret;
  354. ret = cht_wc_extcon_find_role_sw(ext);
  355. if (ret)
  356. return ret;
  357. ret = devm_add_action_or_reset(ext->dev, cht_wc_extcon_put_role_sw, ext);
  358. if (ret)
  359. return ret;
  360. /*
  361. * On x86/ACPI platforms the regulator <-> consumer link is provided
  362. * by platform_data passed to the regulator driver. This means that
  363. * this info is not available before the regulator driver has bound.
  364. * Use devm_regulator_get_optional() to avoid getting a dummy
  365. * regulator and wait for the regulator to show up if necessary.
  366. */
  367. ext->vbus_boost = devm_regulator_get_optional(ext->dev, "vbus");
  368. if (IS_ERR(ext->vbus_boost)) {
  369. ret = PTR_ERR(ext->vbus_boost);
  370. if (ret == -ENODEV)
  371. ret = -EPROBE_DEFER;
  372. return dev_err_probe(ext->dev, ret, "getting Vbus regulator");
  373. }
  374. return 0;
  375. }
  376. static int cht_wc_extcon_psy_get_prop(struct power_supply *psy,
  377. enum power_supply_property psp,
  378. union power_supply_propval *val)
  379. {
  380. struct cht_wc_extcon_data *ext = power_supply_get_drvdata(psy);
  381. switch (psp) {
  382. case POWER_SUPPLY_PROP_USB_TYPE:
  383. val->intval = ext->usb_type;
  384. break;
  385. case POWER_SUPPLY_PROP_ONLINE:
  386. val->intval = ext->usb_type ? 1 : 0;
  387. break;
  388. default:
  389. return -EINVAL;
  390. }
  391. return 0;
  392. }
  393. static const enum power_supply_property cht_wc_extcon_psy_props[] = {
  394. POWER_SUPPLY_PROP_USB_TYPE,
  395. POWER_SUPPLY_PROP_ONLINE,
  396. };
  397. static const struct power_supply_desc cht_wc_extcon_psy_desc = {
  398. .name = "cht_wcove_pwrsrc",
  399. .type = POWER_SUPPLY_TYPE_USB,
  400. .usb_types = BIT(POWER_SUPPLY_USB_TYPE_SDP) |
  401. BIT(POWER_SUPPLY_USB_TYPE_CDP) |
  402. BIT(POWER_SUPPLY_USB_TYPE_DCP) |
  403. BIT(POWER_SUPPLY_USB_TYPE_ACA) |
  404. BIT(POWER_SUPPLY_USB_TYPE_UNKNOWN),
  405. .properties = cht_wc_extcon_psy_props,
  406. .num_properties = ARRAY_SIZE(cht_wc_extcon_psy_props),
  407. .get_property = cht_wc_extcon_psy_get_prop,
  408. };
  409. static int cht_wc_extcon_register_psy(struct cht_wc_extcon_data *ext)
  410. {
  411. struct power_supply_config psy_cfg = { .drv_data = ext };
  412. ext->psy = devm_power_supply_register(ext->dev,
  413. &cht_wc_extcon_psy_desc,
  414. &psy_cfg);
  415. return PTR_ERR_OR_ZERO(ext->psy);
  416. }
  417. static int cht_wc_extcon_probe(struct platform_device *pdev)
  418. {
  419. struct intel_soc_pmic *pmic = dev_get_drvdata(pdev->dev.parent);
  420. struct cht_wc_extcon_data *ext;
  421. unsigned long mask = ~(CHT_WC_PWRSRC_VBUS | CHT_WC_PWRSRC_USBID_MASK);
  422. int pwrsrc_sts, id;
  423. int irq, ret;
  424. irq = platform_get_irq(pdev, 0);
  425. if (irq < 0)
  426. return irq;
  427. ext = devm_kzalloc(&pdev->dev, sizeof(*ext), GFP_KERNEL);
  428. if (!ext)
  429. return -ENOMEM;
  430. ext->dev = &pdev->dev;
  431. ext->regmap = pmic->regmap;
  432. ext->previous_cable = EXTCON_NONE;
  433. /* Initialize extcon device */
  434. ext->edev = devm_extcon_dev_allocate(ext->dev, cht_wc_extcon_cables);
  435. if (IS_ERR(ext->edev))
  436. return PTR_ERR(ext->edev);
  437. switch (pmic->cht_wc_model) {
  438. case INTEL_CHT_WC_GPD_WIN_POCKET:
  439. /*
  440. * When a host-cable is detected the BIOS enables an external 5v boost
  441. * converter to power connected devices there are 2 problems with this:
  442. * 1) This gets seen by the external battery charger as a valid Vbus
  443. * supply and it then tries to feed Vsys from this creating a
  444. * feedback loop which causes aprox. 300 mA extra battery drain
  445. * (and unless we drive the external-charger-disable pin high it
  446. * also tries to charge the battery causing even more feedback).
  447. * 2) This gets seen by the pwrsrc block as a SDP USB Vbus supply
  448. * Since the external battery charger has its own 5v boost converter
  449. * which does not have these issues, we simply turn the separate
  450. * external 5v boost converter off and leave it off entirely.
  451. */
  452. cht_wc_extcon_set_5v_boost(ext, false);
  453. break;
  454. case INTEL_CHT_WC_LENOVO_YOGABOOK1:
  455. case INTEL_CHT_WC_LENOVO_YT3_X90:
  456. /* Do this first, as it may very well return -EPROBE_DEFER. */
  457. ret = cht_wc_extcon_get_role_sw_and_regulator(ext);
  458. if (ret)
  459. return ret;
  460. /*
  461. * The bq25890 used here relies on this driver's BC-1.2 charger
  462. * detection, and the bq25890 driver expect this info to be
  463. * available through a parent power_supply class device which
  464. * models the detected charger (idem to how the Type-C TCPM code
  465. * registers a power_supply classdev for the connected charger).
  466. */
  467. ret = cht_wc_extcon_register_psy(ext);
  468. if (ret)
  469. return ret;
  470. break;
  471. case INTEL_CHT_WC_XIAOMI_MIPAD2:
  472. ret = cht_wc_extcon_get_role_sw_and_regulator(ext);
  473. if (ret)
  474. return ret;
  475. break;
  476. default:
  477. break;
  478. }
  479. /* Enable sw control */
  480. ret = cht_wc_extcon_sw_control(ext, true);
  481. if (ret)
  482. goto disable_sw_control;
  483. /* Disable charging by external battery charger */
  484. cht_wc_extcon_enable_charging(ext, false);
  485. /* Register extcon device */
  486. ret = devm_extcon_dev_register(ext->dev, ext->edev);
  487. if (ret) {
  488. dev_err(ext->dev, "Error registering extcon device: %d\n", ret);
  489. goto disable_sw_control;
  490. }
  491. ret = regmap_read(ext->regmap, CHT_WC_PWRSRC_STS, &pwrsrc_sts);
  492. if (ret) {
  493. dev_err(ext->dev, "Error reading pwrsrc status: %d\n", ret);
  494. goto disable_sw_control;
  495. }
  496. /*
  497. * If no USB host or device connected, route D+ and D- to PMIC for
  498. * initial charger detection
  499. */
  500. id = cht_wc_extcon_get_id(ext, pwrsrc_sts);
  501. if (id != INTEL_USB_ID_GND)
  502. cht_wc_extcon_set_phymux(ext, MUX_SEL_PMIC);
  503. /* Get initial state */
  504. cht_wc_extcon_pwrsrc_event(ext);
  505. ret = devm_request_threaded_irq(ext->dev, irq, NULL, cht_wc_extcon_isr,
  506. IRQF_ONESHOT, pdev->name, ext);
  507. if (ret) {
  508. dev_err(ext->dev, "Error requesting interrupt: %d\n", ret);
  509. goto disable_sw_control;
  510. }
  511. /* Unmask irqs */
  512. ret = regmap_write(ext->regmap, CHT_WC_PWRSRC_IRQ_MASK, mask);
  513. if (ret) {
  514. dev_err(ext->dev, "Error writing irq-mask: %d\n", ret);
  515. goto disable_sw_control;
  516. }
  517. platform_set_drvdata(pdev, ext);
  518. return 0;
  519. disable_sw_control:
  520. cht_wc_extcon_sw_control(ext, false);
  521. return ret;
  522. }
  523. static void cht_wc_extcon_remove(struct platform_device *pdev)
  524. {
  525. struct cht_wc_extcon_data *ext = platform_get_drvdata(pdev);
  526. cht_wc_extcon_sw_control(ext, false);
  527. }
  528. static const struct platform_device_id cht_wc_extcon_table[] = {
  529. { .name = "cht_wcove_pwrsrc" },
  530. {},
  531. };
  532. MODULE_DEVICE_TABLE(platform, cht_wc_extcon_table);
  533. static struct platform_driver cht_wc_extcon_driver = {
  534. .probe = cht_wc_extcon_probe,
  535. .remove_new = cht_wc_extcon_remove,
  536. .id_table = cht_wc_extcon_table,
  537. .driver = {
  538. .name = "cht_wcove_pwrsrc",
  539. },
  540. };
  541. module_platform_driver(cht_wc_extcon_driver);
  542. MODULE_DESCRIPTION("Intel Cherrytrail Whiskey Cove PMIC extcon driver");
  543. MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>");
  544. MODULE_LICENSE("GPL v2");