mtk_cec.c 6.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2014 MediaTek Inc.
  4. * Author: Jie Qiu <jie.qiu@mediatek.com>
  5. */
  6. #include <linux/clk.h>
  7. #include <linux/delay.h>
  8. #include <linux/io.h>
  9. #include <linux/interrupt.h>
  10. #include <linux/module.h>
  11. #include <linux/mod_devicetable.h>
  12. #include <linux/platform_device.h>
  13. #include "mtk_cec.h"
  14. #include "mtk_hdmi.h"
  15. #include "mtk_drm_drv.h"
  16. #define TR_CONFIG 0x00
  17. #define CLEAR_CEC_IRQ BIT(15)
  18. #define CEC_CKGEN 0x04
  19. #define CEC_32K_PDN BIT(19)
  20. #define PDN BIT(16)
  21. #define RX_EVENT 0x54
  22. #define HDMI_PORD BIT(25)
  23. #define HDMI_HTPLG BIT(24)
  24. #define HDMI_PORD_INT_EN BIT(9)
  25. #define HDMI_HTPLG_INT_EN BIT(8)
  26. #define RX_GEN_WD 0x58
  27. #define HDMI_PORD_INT_32K_STATUS BIT(26)
  28. #define RX_RISC_INT_32K_STATUS BIT(25)
  29. #define HDMI_HTPLG_INT_32K_STATUS BIT(24)
  30. #define HDMI_PORD_INT_32K_CLR BIT(18)
  31. #define RX_INT_32K_CLR BIT(17)
  32. #define HDMI_HTPLG_INT_32K_CLR BIT(16)
  33. #define HDMI_PORD_INT_32K_STA_MASK BIT(10)
  34. #define RX_RISC_INT_32K_STA_MASK BIT(9)
  35. #define HDMI_HTPLG_INT_32K_STA_MASK BIT(8)
  36. #define HDMI_PORD_INT_32K_EN BIT(2)
  37. #define RX_INT_32K_EN BIT(1)
  38. #define HDMI_HTPLG_INT_32K_EN BIT(0)
  39. #define NORMAL_INT_CTRL 0x5C
  40. #define HDMI_HTPLG_INT_STA BIT(0)
  41. #define HDMI_PORD_INT_STA BIT(1)
  42. #define HDMI_HTPLG_INT_CLR BIT(16)
  43. #define HDMI_PORD_INT_CLR BIT(17)
  44. #define HDMI_FULL_INT_CLR BIT(20)
  45. struct mtk_cec {
  46. void __iomem *regs;
  47. struct clk *clk;
  48. int irq;
  49. bool hpd;
  50. void (*hpd_event)(bool hpd, struct device *dev);
  51. struct device *hdmi_dev;
  52. spinlock_t lock;
  53. };
  54. static void mtk_cec_clear_bits(struct mtk_cec *cec, unsigned int offset,
  55. unsigned int bits)
  56. {
  57. void __iomem *reg = cec->regs + offset;
  58. u32 tmp;
  59. tmp = readl(reg);
  60. tmp &= ~bits;
  61. writel(tmp, reg);
  62. }
  63. static void mtk_cec_set_bits(struct mtk_cec *cec, unsigned int offset,
  64. unsigned int bits)
  65. {
  66. void __iomem *reg = cec->regs + offset;
  67. u32 tmp;
  68. tmp = readl(reg);
  69. tmp |= bits;
  70. writel(tmp, reg);
  71. }
  72. static void mtk_cec_mask(struct mtk_cec *cec, unsigned int offset,
  73. unsigned int val, unsigned int mask)
  74. {
  75. u32 tmp = readl(cec->regs + offset) & ~mask;
  76. tmp |= val & mask;
  77. writel(tmp, cec->regs + offset);
  78. }
  79. void mtk_cec_set_hpd_event(struct device *dev,
  80. void (*hpd_event)(bool hpd, struct device *dev),
  81. struct device *hdmi_dev)
  82. {
  83. struct mtk_cec *cec = dev_get_drvdata(dev);
  84. unsigned long flags;
  85. spin_lock_irqsave(&cec->lock, flags);
  86. cec->hdmi_dev = hdmi_dev;
  87. cec->hpd_event = hpd_event;
  88. spin_unlock_irqrestore(&cec->lock, flags);
  89. }
  90. bool mtk_cec_hpd_high(struct device *dev)
  91. {
  92. struct mtk_cec *cec = dev_get_drvdata(dev);
  93. unsigned int status;
  94. status = readl(cec->regs + RX_EVENT);
  95. return (status & (HDMI_PORD | HDMI_HTPLG)) == (HDMI_PORD | HDMI_HTPLG);
  96. }
  97. static void mtk_cec_htplg_irq_init(struct mtk_cec *cec)
  98. {
  99. mtk_cec_mask(cec, CEC_CKGEN, 0 | CEC_32K_PDN, PDN | CEC_32K_PDN);
  100. mtk_cec_set_bits(cec, RX_GEN_WD, HDMI_PORD_INT_32K_CLR |
  101. RX_INT_32K_CLR | HDMI_HTPLG_INT_32K_CLR);
  102. mtk_cec_mask(cec, RX_GEN_WD, 0, HDMI_PORD_INT_32K_CLR | RX_INT_32K_CLR |
  103. HDMI_HTPLG_INT_32K_CLR | HDMI_PORD_INT_32K_EN |
  104. RX_INT_32K_EN | HDMI_HTPLG_INT_32K_EN);
  105. }
  106. static void mtk_cec_htplg_irq_enable(struct mtk_cec *cec)
  107. {
  108. mtk_cec_set_bits(cec, RX_EVENT, HDMI_PORD_INT_EN | HDMI_HTPLG_INT_EN);
  109. }
  110. static void mtk_cec_htplg_irq_disable(struct mtk_cec *cec)
  111. {
  112. mtk_cec_clear_bits(cec, RX_EVENT, HDMI_PORD_INT_EN | HDMI_HTPLG_INT_EN);
  113. }
  114. static void mtk_cec_clear_htplg_irq(struct mtk_cec *cec)
  115. {
  116. mtk_cec_set_bits(cec, TR_CONFIG, CLEAR_CEC_IRQ);
  117. mtk_cec_set_bits(cec, NORMAL_INT_CTRL, HDMI_HTPLG_INT_CLR |
  118. HDMI_PORD_INT_CLR | HDMI_FULL_INT_CLR);
  119. mtk_cec_set_bits(cec, RX_GEN_WD, HDMI_PORD_INT_32K_CLR |
  120. RX_INT_32K_CLR | HDMI_HTPLG_INT_32K_CLR);
  121. usleep_range(5, 10);
  122. mtk_cec_clear_bits(cec, NORMAL_INT_CTRL, HDMI_HTPLG_INT_CLR |
  123. HDMI_PORD_INT_CLR | HDMI_FULL_INT_CLR);
  124. mtk_cec_clear_bits(cec, TR_CONFIG, CLEAR_CEC_IRQ);
  125. mtk_cec_clear_bits(cec, RX_GEN_WD, HDMI_PORD_INT_32K_CLR |
  126. RX_INT_32K_CLR | HDMI_HTPLG_INT_32K_CLR);
  127. }
  128. static void mtk_cec_hpd_event(struct mtk_cec *cec, bool hpd)
  129. {
  130. void (*hpd_event)(bool hpd, struct device *dev);
  131. struct device *hdmi_dev;
  132. unsigned long flags;
  133. spin_lock_irqsave(&cec->lock, flags);
  134. hpd_event = cec->hpd_event;
  135. hdmi_dev = cec->hdmi_dev;
  136. spin_unlock_irqrestore(&cec->lock, flags);
  137. if (hpd_event)
  138. hpd_event(hpd, hdmi_dev);
  139. }
  140. static irqreturn_t mtk_cec_htplg_isr_thread(int irq, void *arg)
  141. {
  142. struct device *dev = arg;
  143. struct mtk_cec *cec = dev_get_drvdata(dev);
  144. bool hpd;
  145. mtk_cec_clear_htplg_irq(cec);
  146. hpd = mtk_cec_hpd_high(dev);
  147. if (cec->hpd != hpd) {
  148. dev_dbg(dev, "hotplug event! cur hpd = %d, hpd = %d\n",
  149. cec->hpd, hpd);
  150. cec->hpd = hpd;
  151. mtk_cec_hpd_event(cec, hpd);
  152. }
  153. return IRQ_HANDLED;
  154. }
  155. static int mtk_cec_probe(struct platform_device *pdev)
  156. {
  157. struct device *dev = &pdev->dev;
  158. struct mtk_cec *cec;
  159. int ret;
  160. cec = devm_kzalloc(dev, sizeof(*cec), GFP_KERNEL);
  161. if (!cec)
  162. return -ENOMEM;
  163. platform_set_drvdata(pdev, cec);
  164. spin_lock_init(&cec->lock);
  165. cec->regs = devm_platform_ioremap_resource(pdev, 0);
  166. if (IS_ERR(cec->regs))
  167. return dev_err_probe(dev, PTR_ERR(cec->regs),
  168. "Failed to ioremap cec\n");
  169. cec->clk = devm_clk_get(dev, NULL);
  170. if (IS_ERR(cec->clk))
  171. return dev_err_probe(dev, PTR_ERR(cec->clk),
  172. "Failed to get cec clock\n");
  173. cec->irq = platform_get_irq(pdev, 0);
  174. if (cec->irq < 0)
  175. return cec->irq;
  176. ret = devm_request_threaded_irq(dev, cec->irq, NULL,
  177. mtk_cec_htplg_isr_thread,
  178. IRQF_SHARED | IRQF_TRIGGER_LOW |
  179. IRQF_ONESHOT, "hdmi hpd", dev);
  180. if (ret)
  181. return dev_err_probe(dev, ret, "Failed to register cec irq\n");
  182. ret = clk_prepare_enable(cec->clk);
  183. if (ret)
  184. return dev_err_probe(dev, ret, "Failed to enable cec clock\n");
  185. mtk_cec_htplg_irq_init(cec);
  186. mtk_cec_htplg_irq_enable(cec);
  187. return 0;
  188. }
  189. static void mtk_cec_remove(struct platform_device *pdev)
  190. {
  191. struct mtk_cec *cec = platform_get_drvdata(pdev);
  192. mtk_cec_htplg_irq_disable(cec);
  193. clk_disable_unprepare(cec->clk);
  194. }
  195. static const struct of_device_id mtk_cec_of_ids[] = {
  196. { .compatible = "mediatek,mt8173-cec", },
  197. {}
  198. };
  199. MODULE_DEVICE_TABLE(of, mtk_cec_of_ids);
  200. struct platform_driver mtk_cec_driver = {
  201. .probe = mtk_cec_probe,
  202. .remove_new = mtk_cec_remove,
  203. .driver = {
  204. .name = "mediatek-cec",
  205. .of_match_table = mtk_cec_of_ids,
  206. },
  207. };