riscv.h 694 B

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2022, NVIDIA Corporation.
  4. */
  5. #ifndef DRM_TEGRA_RISCV_H
  6. #define DRM_TEGRA_RISCV_H
  7. struct tegra_drm_riscv_descriptor {
  8. u32 manifest_offset;
  9. u32 code_offset;
  10. u32 code_size;
  11. u32 data_offset;
  12. u32 data_size;
  13. };
  14. struct tegra_drm_riscv {
  15. /* User initializes */
  16. struct device *dev;
  17. void __iomem *regs;
  18. struct tegra_drm_riscv_descriptor bl_desc;
  19. struct tegra_drm_riscv_descriptor os_desc;
  20. };
  21. int tegra_drm_riscv_read_descriptors(struct tegra_drm_riscv *riscv);
  22. int tegra_drm_riscv_boot_bootrom(struct tegra_drm_riscv *riscv, phys_addr_t image_address,
  23. u32 gscid, const struct tegra_drm_riscv_descriptor *desc);
  24. #endif