industrialio-buffer-dmaengine.c 9.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright 2014-2015 Analog Devices Inc.
  4. * Author: Lars-Peter Clausen <lars@metafoo.de>
  5. */
  6. #include <linux/slab.h>
  7. #include <linux/kernel.h>
  8. #include <linux/dmaengine.h>
  9. #include <linux/dma-mapping.h>
  10. #include <linux/spinlock.h>
  11. #include <linux/err.h>
  12. #include <linux/module.h>
  13. #include <linux/iio/iio.h>
  14. #include <linux/iio/sysfs.h>
  15. #include <linux/iio/buffer.h>
  16. #include <linux/iio/buffer_impl.h>
  17. #include <linux/iio/buffer-dma.h>
  18. #include <linux/iio/buffer-dmaengine.h>
  19. /*
  20. * The IIO DMAengine buffer combines the generic IIO DMA buffer infrastructure
  21. * with the DMAengine framework. The generic IIO DMA buffer infrastructure is
  22. * used to manage the buffer memory and implement the IIO buffer operations
  23. * while the DMAengine framework is used to perform the DMA transfers. Combined
  24. * this results in a device independent fully functional DMA buffer
  25. * implementation that can be used by device drivers for peripherals which are
  26. * connected to a DMA controller which has a DMAengine driver implementation.
  27. */
  28. struct dmaengine_buffer {
  29. struct iio_dma_buffer_queue queue;
  30. struct dma_chan *chan;
  31. struct list_head active;
  32. size_t align;
  33. size_t max_size;
  34. };
  35. static struct dmaengine_buffer *iio_buffer_to_dmaengine_buffer(
  36. struct iio_buffer *buffer)
  37. {
  38. return container_of(buffer, struct dmaengine_buffer, queue.buffer);
  39. }
  40. static void iio_dmaengine_buffer_block_done(void *data,
  41. const struct dmaengine_result *result)
  42. {
  43. struct iio_dma_buffer_block *block = data;
  44. unsigned long flags;
  45. spin_lock_irqsave(&block->queue->list_lock, flags);
  46. list_del(&block->head);
  47. spin_unlock_irqrestore(&block->queue->list_lock, flags);
  48. block->bytes_used -= result->residue;
  49. iio_dma_buffer_block_done(block);
  50. }
  51. static int iio_dmaengine_buffer_submit_block(struct iio_dma_buffer_queue *queue,
  52. struct iio_dma_buffer_block *block)
  53. {
  54. struct dmaengine_buffer *dmaengine_buffer =
  55. iio_buffer_to_dmaengine_buffer(&queue->buffer);
  56. struct dma_async_tx_descriptor *desc;
  57. enum dma_transfer_direction dma_dir;
  58. struct scatterlist *sgl;
  59. struct dma_vec *vecs;
  60. size_t max_size;
  61. dma_cookie_t cookie;
  62. size_t len_total;
  63. unsigned int i;
  64. int nents;
  65. max_size = min(block->size, dmaengine_buffer->max_size);
  66. max_size = round_down(max_size, dmaengine_buffer->align);
  67. if (queue->buffer.direction == IIO_BUFFER_DIRECTION_IN)
  68. dma_dir = DMA_DEV_TO_MEM;
  69. else
  70. dma_dir = DMA_MEM_TO_DEV;
  71. if (block->sg_table) {
  72. sgl = block->sg_table->sgl;
  73. nents = sg_nents_for_len(sgl, block->bytes_used);
  74. if (nents < 0)
  75. return nents;
  76. vecs = kmalloc_array(nents, sizeof(*vecs), GFP_ATOMIC);
  77. if (!vecs)
  78. return -ENOMEM;
  79. len_total = block->bytes_used;
  80. for (i = 0; i < nents; i++) {
  81. vecs[i].addr = sg_dma_address(sgl);
  82. vecs[i].len = min(sg_dma_len(sgl), len_total);
  83. len_total -= vecs[i].len;
  84. sgl = sg_next(sgl);
  85. }
  86. desc = dmaengine_prep_peripheral_dma_vec(dmaengine_buffer->chan,
  87. vecs, nents, dma_dir,
  88. DMA_PREP_INTERRUPT);
  89. kfree(vecs);
  90. } else {
  91. max_size = min(block->size, dmaengine_buffer->max_size);
  92. max_size = round_down(max_size, dmaengine_buffer->align);
  93. if (queue->buffer.direction == IIO_BUFFER_DIRECTION_IN)
  94. block->bytes_used = max_size;
  95. if (!block->bytes_used || block->bytes_used > max_size)
  96. return -EINVAL;
  97. desc = dmaengine_prep_slave_single(dmaengine_buffer->chan,
  98. block->phys_addr,
  99. block->bytes_used,
  100. dma_dir,
  101. DMA_PREP_INTERRUPT);
  102. }
  103. if (!desc)
  104. return -ENOMEM;
  105. desc->callback_result = iio_dmaengine_buffer_block_done;
  106. desc->callback_param = block;
  107. cookie = dmaengine_submit(desc);
  108. if (dma_submit_error(cookie))
  109. return dma_submit_error(cookie);
  110. spin_lock_irq(&dmaengine_buffer->queue.list_lock);
  111. list_add_tail(&block->head, &dmaengine_buffer->active);
  112. spin_unlock_irq(&dmaengine_buffer->queue.list_lock);
  113. dma_async_issue_pending(dmaengine_buffer->chan);
  114. return 0;
  115. }
  116. static void iio_dmaengine_buffer_abort(struct iio_dma_buffer_queue *queue)
  117. {
  118. struct dmaengine_buffer *dmaengine_buffer =
  119. iio_buffer_to_dmaengine_buffer(&queue->buffer);
  120. dmaengine_terminate_sync(dmaengine_buffer->chan);
  121. iio_dma_buffer_block_list_abort(queue, &dmaengine_buffer->active);
  122. }
  123. static void iio_dmaengine_buffer_release(struct iio_buffer *buf)
  124. {
  125. struct dmaengine_buffer *dmaengine_buffer =
  126. iio_buffer_to_dmaengine_buffer(buf);
  127. iio_dma_buffer_release(&dmaengine_buffer->queue);
  128. kfree(dmaengine_buffer);
  129. }
  130. static const struct iio_buffer_access_funcs iio_dmaengine_buffer_ops = {
  131. .read = iio_dma_buffer_read,
  132. .write = iio_dma_buffer_write,
  133. .set_bytes_per_datum = iio_dma_buffer_set_bytes_per_datum,
  134. .set_length = iio_dma_buffer_set_length,
  135. .request_update = iio_dma_buffer_request_update,
  136. .enable = iio_dma_buffer_enable,
  137. .disable = iio_dma_buffer_disable,
  138. .data_available = iio_dma_buffer_usage,
  139. .space_available = iio_dma_buffer_usage,
  140. .release = iio_dmaengine_buffer_release,
  141. .enqueue_dmabuf = iio_dma_buffer_enqueue_dmabuf,
  142. .attach_dmabuf = iio_dma_buffer_attach_dmabuf,
  143. .detach_dmabuf = iio_dma_buffer_detach_dmabuf,
  144. .lock_queue = iio_dma_buffer_lock_queue,
  145. .unlock_queue = iio_dma_buffer_unlock_queue,
  146. .modes = INDIO_BUFFER_HARDWARE,
  147. .flags = INDIO_BUFFER_FLAG_FIXED_WATERMARK,
  148. };
  149. static const struct iio_dma_buffer_ops iio_dmaengine_default_ops = {
  150. .submit = iio_dmaengine_buffer_submit_block,
  151. .abort = iio_dmaengine_buffer_abort,
  152. };
  153. static ssize_t iio_dmaengine_buffer_get_length_align(struct device *dev,
  154. struct device_attribute *attr, char *buf)
  155. {
  156. struct iio_buffer *buffer = to_iio_dev_attr(attr)->buffer;
  157. struct dmaengine_buffer *dmaengine_buffer =
  158. iio_buffer_to_dmaengine_buffer(buffer);
  159. return sysfs_emit(buf, "%zu\n", dmaengine_buffer->align);
  160. }
  161. static IIO_DEVICE_ATTR(length_align_bytes, 0444,
  162. iio_dmaengine_buffer_get_length_align, NULL, 0);
  163. static const struct iio_dev_attr *iio_dmaengine_buffer_attrs[] = {
  164. &iio_dev_attr_length_align_bytes,
  165. NULL,
  166. };
  167. /**
  168. * iio_dmaengine_buffer_alloc() - Allocate new buffer which uses DMAengine
  169. * @dev: Parent device for the buffer
  170. * @channel: DMA channel name, typically "rx".
  171. *
  172. * This allocates a new IIO buffer which internally uses the DMAengine framework
  173. * to perform its transfers. The parent device will be used to request the DMA
  174. * channel.
  175. *
  176. * Once done using the buffer iio_dmaengine_buffer_free() should be used to
  177. * release it.
  178. */
  179. static struct iio_buffer *iio_dmaengine_buffer_alloc(struct device *dev,
  180. const char *channel)
  181. {
  182. struct dmaengine_buffer *dmaengine_buffer;
  183. unsigned int width, src_width, dest_width;
  184. struct dma_slave_caps caps;
  185. struct dma_chan *chan;
  186. int ret;
  187. dmaengine_buffer = kzalloc(sizeof(*dmaengine_buffer), GFP_KERNEL);
  188. if (!dmaengine_buffer)
  189. return ERR_PTR(-ENOMEM);
  190. chan = dma_request_chan(dev, channel);
  191. if (IS_ERR(chan)) {
  192. ret = PTR_ERR(chan);
  193. goto err_free;
  194. }
  195. ret = dma_get_slave_caps(chan, &caps);
  196. if (ret < 0)
  197. goto err_release;
  198. /* Needs to be aligned to the maximum of the minimums */
  199. if (caps.src_addr_widths)
  200. src_width = __ffs(caps.src_addr_widths);
  201. else
  202. src_width = 1;
  203. if (caps.dst_addr_widths)
  204. dest_width = __ffs(caps.dst_addr_widths);
  205. else
  206. dest_width = 1;
  207. width = max(src_width, dest_width);
  208. INIT_LIST_HEAD(&dmaengine_buffer->active);
  209. dmaengine_buffer->chan = chan;
  210. dmaengine_buffer->align = width;
  211. dmaengine_buffer->max_size = dma_get_max_seg_size(chan->device->dev);
  212. iio_dma_buffer_init(&dmaengine_buffer->queue, chan->device->dev,
  213. &iio_dmaengine_default_ops);
  214. dmaengine_buffer->queue.buffer.attrs = iio_dmaengine_buffer_attrs;
  215. dmaengine_buffer->queue.buffer.access = &iio_dmaengine_buffer_ops;
  216. return &dmaengine_buffer->queue.buffer;
  217. err_release:
  218. dma_release_channel(chan);
  219. err_free:
  220. kfree(dmaengine_buffer);
  221. return ERR_PTR(ret);
  222. }
  223. /**
  224. * iio_dmaengine_buffer_free() - Free dmaengine buffer
  225. * @buffer: Buffer to free
  226. *
  227. * Frees a buffer previously allocated with iio_dmaengine_buffer_alloc().
  228. */
  229. void iio_dmaengine_buffer_free(struct iio_buffer *buffer)
  230. {
  231. struct dmaengine_buffer *dmaengine_buffer =
  232. iio_buffer_to_dmaengine_buffer(buffer);
  233. iio_dma_buffer_exit(&dmaengine_buffer->queue);
  234. dma_release_channel(dmaengine_buffer->chan);
  235. iio_buffer_put(buffer);
  236. }
  237. EXPORT_SYMBOL_NS_GPL(iio_dmaengine_buffer_free, IIO_DMAENGINE_BUFFER);
  238. struct iio_buffer *iio_dmaengine_buffer_setup_ext(struct device *dev,
  239. struct iio_dev *indio_dev,
  240. const char *channel,
  241. enum iio_buffer_direction dir)
  242. {
  243. struct iio_buffer *buffer;
  244. int ret;
  245. buffer = iio_dmaengine_buffer_alloc(dev, channel);
  246. if (IS_ERR(buffer))
  247. return ERR_CAST(buffer);
  248. indio_dev->modes |= INDIO_BUFFER_HARDWARE;
  249. buffer->direction = dir;
  250. ret = iio_device_attach_buffer(indio_dev, buffer);
  251. if (ret) {
  252. iio_dmaengine_buffer_free(buffer);
  253. return ERR_PTR(ret);
  254. }
  255. return buffer;
  256. }
  257. EXPORT_SYMBOL_NS_GPL(iio_dmaengine_buffer_setup_ext, IIO_DMAENGINE_BUFFER);
  258. static void __devm_iio_dmaengine_buffer_free(void *buffer)
  259. {
  260. iio_dmaengine_buffer_free(buffer);
  261. }
  262. /**
  263. * devm_iio_dmaengine_buffer_setup_ext() - Setup a DMA buffer for an IIO device
  264. * @dev: Parent device for the buffer
  265. * @indio_dev: IIO device to which to attach this buffer.
  266. * @channel: DMA channel name, typically "rx".
  267. * @dir: Direction of buffer (in or out)
  268. *
  269. * This allocates a new IIO buffer with devm_iio_dmaengine_buffer_alloc()
  270. * and attaches it to an IIO device with iio_device_attach_buffer().
  271. * It also appends the INDIO_BUFFER_HARDWARE mode to the supported modes of the
  272. * IIO device.
  273. */
  274. int devm_iio_dmaengine_buffer_setup_ext(struct device *dev,
  275. struct iio_dev *indio_dev,
  276. const char *channel,
  277. enum iio_buffer_direction dir)
  278. {
  279. struct iio_buffer *buffer;
  280. buffer = iio_dmaengine_buffer_setup_ext(dev, indio_dev, channel, dir);
  281. if (IS_ERR(buffer))
  282. return PTR_ERR(buffer);
  283. return devm_add_action_or_reset(dev, __devm_iio_dmaengine_buffer_free,
  284. buffer);
  285. }
  286. EXPORT_SYMBOL_NS_GPL(devm_iio_dmaengine_buffer_setup_ext, IIO_DMAENGINE_BUFFER);
  287. MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
  288. MODULE_DESCRIPTION("DMA buffer for the IIO framework");
  289. MODULE_LICENSE("GPL");
  290. MODULE_IMPORT_NS(IIO_DMA_BUFFER);