max30102.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * max30102.c - Support for MAX30102 heart rate and pulse oximeter sensor
  4. *
  5. * Copyright (C) 2017 Matt Ranostay <matt.ranostay@konsulko.com>
  6. *
  7. * Support for MAX30105 optical particle sensor
  8. * Copyright (C) 2017 Peter Meerwald-Stadler <pmeerw@pmeerw.net>
  9. *
  10. * 7-bit I2C chip address: 0x57
  11. * TODO: proximity power saving feature
  12. */
  13. #include <linux/module.h>
  14. #include <linux/init.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/delay.h>
  17. #include <linux/err.h>
  18. #include <linux/irq.h>
  19. #include <linux/i2c.h>
  20. #include <linux/mutex.h>
  21. #include <linux/mod_devicetable.h>
  22. #include <linux/regmap.h>
  23. #include <linux/iio/iio.h>
  24. #include <linux/iio/buffer.h>
  25. #include <linux/iio/kfifo_buf.h>
  26. #define MAX30102_REGMAP_NAME "max30102_regmap"
  27. #define MAX30102_DRV_NAME "max30102"
  28. #define MAX30102_PART_NUMBER 0x15
  29. enum max30102_chip_id {
  30. max30102,
  31. max30105,
  32. };
  33. enum max3012_led_idx {
  34. MAX30102_LED_RED,
  35. MAX30102_LED_IR,
  36. MAX30105_LED_GREEN,
  37. };
  38. #define MAX30102_REG_INT_STATUS 0x00
  39. #define MAX30102_REG_INT_STATUS_PWR_RDY BIT(0)
  40. #define MAX30102_REG_INT_STATUS_PROX_INT BIT(4)
  41. #define MAX30102_REG_INT_STATUS_ALC_OVF BIT(5)
  42. #define MAX30102_REG_INT_STATUS_PPG_RDY BIT(6)
  43. #define MAX30102_REG_INT_STATUS_FIFO_RDY BIT(7)
  44. #define MAX30102_REG_INT_ENABLE 0x02
  45. #define MAX30102_REG_INT_ENABLE_PROX_INT_EN BIT(4)
  46. #define MAX30102_REG_INT_ENABLE_ALC_OVF_EN BIT(5)
  47. #define MAX30102_REG_INT_ENABLE_PPG_EN BIT(6)
  48. #define MAX30102_REG_INT_ENABLE_FIFO_EN BIT(7)
  49. #define MAX30102_REG_INT_ENABLE_MASK 0xf0
  50. #define MAX30102_REG_INT_ENABLE_MASK_SHIFT 4
  51. #define MAX30102_REG_FIFO_WR_PTR 0x04
  52. #define MAX30102_REG_FIFO_OVR_CTR 0x05
  53. #define MAX30102_REG_FIFO_RD_PTR 0x06
  54. #define MAX30102_REG_FIFO_DATA 0x07
  55. #define MAX30102_REG_FIFO_DATA_BYTES 3
  56. #define MAX30102_REG_FIFO_CONFIG 0x08
  57. #define MAX30102_REG_FIFO_CONFIG_AVG_4SAMPLES BIT(1)
  58. #define MAX30102_REG_FIFO_CONFIG_AVG_SHIFT 5
  59. #define MAX30102_REG_FIFO_CONFIG_AFULL BIT(0)
  60. #define MAX30102_REG_MODE_CONFIG 0x09
  61. #define MAX30102_REG_MODE_CONFIG_MODE_NONE 0x00
  62. #define MAX30102_REG_MODE_CONFIG_MODE_HR 0x02 /* red LED */
  63. #define MAX30102_REG_MODE_CONFIG_MODE_HR_SPO2 0x03 /* red + IR LED */
  64. #define MAX30102_REG_MODE_CONFIG_MODE_MULTI 0x07 /* multi-LED mode */
  65. #define MAX30102_REG_MODE_CONFIG_MODE_MASK GENMASK(2, 0)
  66. #define MAX30102_REG_MODE_CONFIG_PWR BIT(7)
  67. #define MAX30102_REG_MODE_CONTROL_SLOT21 0x11 /* multi-LED control */
  68. #define MAX30102_REG_MODE_CONTROL_SLOT43 0x12
  69. #define MAX30102_REG_MODE_CONTROL_SLOT_MASK (GENMASK(6, 4) | GENMASK(2, 0))
  70. #define MAX30102_REG_MODE_CONTROL_SLOT_SHIFT 4
  71. #define MAX30102_REG_SPO2_CONFIG 0x0a
  72. #define MAX30102_REG_SPO2_CONFIG_PULSE_411_US 0x03
  73. #define MAX30102_REG_SPO2_CONFIG_SR_400HZ 0x03
  74. #define MAX30102_REG_SPO2_CONFIG_SR_MASK 0x07
  75. #define MAX30102_REG_SPO2_CONFIG_SR_MASK_SHIFT 2
  76. #define MAX30102_REG_SPO2_CONFIG_ADC_4096_STEPS BIT(0)
  77. #define MAX30102_REG_SPO2_CONFIG_ADC_MASK_SHIFT 5
  78. #define MAX30102_REG_RED_LED_CONFIG 0x0c
  79. #define MAX30102_REG_IR_LED_CONFIG 0x0d
  80. #define MAX30105_REG_GREEN_LED_CONFIG 0x0e
  81. #define MAX30102_REG_TEMP_CONFIG 0x21
  82. #define MAX30102_REG_TEMP_CONFIG_TEMP_EN BIT(0)
  83. #define MAX30102_REG_TEMP_INTEGER 0x1f
  84. #define MAX30102_REG_TEMP_FRACTION 0x20
  85. #define MAX30102_REG_REV_ID 0xfe
  86. #define MAX30102_REG_PART_ID 0xff
  87. struct max30102_data {
  88. struct i2c_client *client;
  89. struct iio_dev *indio_dev;
  90. struct mutex lock;
  91. struct regmap *regmap;
  92. enum max30102_chip_id chip_id;
  93. u8 buffer[12];
  94. __be32 processed_buffer[3]; /* 3 x 18-bit (padded to 32-bits) */
  95. };
  96. static const struct regmap_config max30102_regmap_config = {
  97. .name = MAX30102_REGMAP_NAME,
  98. .reg_bits = 8,
  99. .val_bits = 8,
  100. };
  101. static const unsigned long max30102_scan_masks[] = {
  102. BIT(MAX30102_LED_RED) | BIT(MAX30102_LED_IR),
  103. 0
  104. };
  105. static const unsigned long max30105_scan_masks[] = {
  106. BIT(MAX30102_LED_RED) | BIT(MAX30102_LED_IR),
  107. BIT(MAX30102_LED_RED) | BIT(MAX30102_LED_IR) |
  108. BIT(MAX30105_LED_GREEN),
  109. 0
  110. };
  111. #define MAX30102_INTENSITY_CHANNEL(_si, _mod) { \
  112. .type = IIO_INTENSITY, \
  113. .channel2 = _mod, \
  114. .modified = 1, \
  115. .scan_index = _si, \
  116. .scan_type = { \
  117. .sign = 'u', \
  118. .shift = 8, \
  119. .realbits = 18, \
  120. .storagebits = 32, \
  121. .endianness = IIO_BE, \
  122. }, \
  123. }
  124. static const struct iio_chan_spec max30102_channels[] = {
  125. MAX30102_INTENSITY_CHANNEL(MAX30102_LED_RED, IIO_MOD_LIGHT_RED),
  126. MAX30102_INTENSITY_CHANNEL(MAX30102_LED_IR, IIO_MOD_LIGHT_IR),
  127. {
  128. .type = IIO_TEMP,
  129. .info_mask_separate =
  130. BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
  131. .scan_index = -1,
  132. },
  133. };
  134. static const struct iio_chan_spec max30105_channels[] = {
  135. MAX30102_INTENSITY_CHANNEL(MAX30102_LED_RED, IIO_MOD_LIGHT_RED),
  136. MAX30102_INTENSITY_CHANNEL(MAX30102_LED_IR, IIO_MOD_LIGHT_IR),
  137. MAX30102_INTENSITY_CHANNEL(MAX30105_LED_GREEN, IIO_MOD_LIGHT_GREEN),
  138. {
  139. .type = IIO_TEMP,
  140. .info_mask_separate =
  141. BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
  142. .scan_index = -1,
  143. },
  144. };
  145. static int max30102_set_power(struct max30102_data *data, bool en)
  146. {
  147. return regmap_update_bits(data->regmap, MAX30102_REG_MODE_CONFIG,
  148. MAX30102_REG_MODE_CONFIG_PWR,
  149. en ? 0 : MAX30102_REG_MODE_CONFIG_PWR);
  150. }
  151. static int max30102_set_powermode(struct max30102_data *data, u8 mode, bool en)
  152. {
  153. u8 reg = mode;
  154. if (!en)
  155. reg |= MAX30102_REG_MODE_CONFIG_PWR;
  156. return regmap_update_bits(data->regmap, MAX30102_REG_MODE_CONFIG,
  157. MAX30102_REG_MODE_CONFIG_PWR |
  158. MAX30102_REG_MODE_CONFIG_MODE_MASK, reg);
  159. }
  160. #define MAX30102_MODE_CONTROL_LED_SLOTS(slot2, slot1) \
  161. ((slot2 << MAX30102_REG_MODE_CONTROL_SLOT_SHIFT) | slot1)
  162. static int max30102_buffer_postenable(struct iio_dev *indio_dev)
  163. {
  164. struct max30102_data *data = iio_priv(indio_dev);
  165. int ret;
  166. u8 reg;
  167. switch (*indio_dev->active_scan_mask) {
  168. case BIT(MAX30102_LED_RED) | BIT(MAX30102_LED_IR):
  169. reg = MAX30102_REG_MODE_CONFIG_MODE_HR_SPO2;
  170. break;
  171. case BIT(MAX30102_LED_RED) | BIT(MAX30102_LED_IR) |
  172. BIT(MAX30105_LED_GREEN):
  173. ret = regmap_update_bits(data->regmap,
  174. MAX30102_REG_MODE_CONTROL_SLOT21,
  175. MAX30102_REG_MODE_CONTROL_SLOT_MASK,
  176. MAX30102_MODE_CONTROL_LED_SLOTS(2, 1));
  177. if (ret)
  178. return ret;
  179. ret = regmap_update_bits(data->regmap,
  180. MAX30102_REG_MODE_CONTROL_SLOT43,
  181. MAX30102_REG_MODE_CONTROL_SLOT_MASK,
  182. MAX30102_MODE_CONTROL_LED_SLOTS(0, 3));
  183. if (ret)
  184. return ret;
  185. reg = MAX30102_REG_MODE_CONFIG_MODE_MULTI;
  186. break;
  187. default:
  188. return -EINVAL;
  189. }
  190. return max30102_set_powermode(data, reg, true);
  191. }
  192. static int max30102_buffer_predisable(struct iio_dev *indio_dev)
  193. {
  194. struct max30102_data *data = iio_priv(indio_dev);
  195. return max30102_set_powermode(data, MAX30102_REG_MODE_CONFIG_MODE_NONE,
  196. false);
  197. }
  198. static const struct iio_buffer_setup_ops max30102_buffer_setup_ops = {
  199. .postenable = max30102_buffer_postenable,
  200. .predisable = max30102_buffer_predisable,
  201. };
  202. static inline int max30102_fifo_count(struct max30102_data *data)
  203. {
  204. unsigned int val;
  205. int ret;
  206. ret = regmap_read(data->regmap, MAX30102_REG_INT_STATUS, &val);
  207. if (ret)
  208. return ret;
  209. /* FIFO has one sample slot left */
  210. if (val & MAX30102_REG_INT_STATUS_FIFO_RDY)
  211. return 1;
  212. return 0;
  213. }
  214. #define MAX30102_COPY_DATA(i) \
  215. memcpy(&data->processed_buffer[(i)], \
  216. &buffer[(i) * MAX30102_REG_FIFO_DATA_BYTES], \
  217. MAX30102_REG_FIFO_DATA_BYTES)
  218. static int max30102_read_measurement(struct max30102_data *data,
  219. unsigned int measurements)
  220. {
  221. int ret;
  222. u8 *buffer = (u8 *) &data->buffer;
  223. ret = i2c_smbus_read_i2c_block_data(data->client,
  224. MAX30102_REG_FIFO_DATA,
  225. measurements *
  226. MAX30102_REG_FIFO_DATA_BYTES,
  227. buffer);
  228. switch (measurements) {
  229. case 3:
  230. MAX30102_COPY_DATA(2);
  231. fallthrough;
  232. case 2:
  233. MAX30102_COPY_DATA(1);
  234. fallthrough;
  235. case 1:
  236. MAX30102_COPY_DATA(0);
  237. break;
  238. default:
  239. return -EINVAL;
  240. }
  241. return (ret == measurements * MAX30102_REG_FIFO_DATA_BYTES) ?
  242. 0 : -EINVAL;
  243. }
  244. static irqreturn_t max30102_interrupt_handler(int irq, void *private)
  245. {
  246. struct iio_dev *indio_dev = private;
  247. struct max30102_data *data = iio_priv(indio_dev);
  248. unsigned int measurements = bitmap_weight(indio_dev->active_scan_mask,
  249. iio_get_masklength(indio_dev));
  250. int ret, cnt = 0;
  251. mutex_lock(&data->lock);
  252. while (cnt || (cnt = max30102_fifo_count(data)) > 0) {
  253. ret = max30102_read_measurement(data, measurements);
  254. if (ret)
  255. break;
  256. iio_push_to_buffers(data->indio_dev, data->processed_buffer);
  257. cnt--;
  258. }
  259. mutex_unlock(&data->lock);
  260. return IRQ_HANDLED;
  261. }
  262. static int max30102_get_current_idx(unsigned int val, int *reg)
  263. {
  264. /* each step is 0.200 mA */
  265. *reg = val / 200;
  266. return *reg > 0xff ? -EINVAL : 0;
  267. }
  268. static int max30102_led_init(struct max30102_data *data)
  269. {
  270. struct device *dev = &data->client->dev;
  271. unsigned int val;
  272. int reg, ret;
  273. ret = device_property_read_u32(dev, "maxim,red-led-current-microamp", &val);
  274. if (ret) {
  275. dev_info(dev, "no red-led-current-microamp set\n");
  276. /* Default to 7 mA RED LED */
  277. val = 7000;
  278. }
  279. ret = max30102_get_current_idx(val, &reg);
  280. if (ret) {
  281. dev_err(dev, "invalid RED LED current setting %d\n", val);
  282. return ret;
  283. }
  284. ret = regmap_write(data->regmap, MAX30102_REG_RED_LED_CONFIG, reg);
  285. if (ret)
  286. return ret;
  287. if (data->chip_id == max30105) {
  288. ret = device_property_read_u32(dev,
  289. "maxim,green-led-current-microamp", &val);
  290. if (ret) {
  291. dev_info(dev, "no green-led-current-microamp set\n");
  292. /* Default to 7 mA green LED */
  293. val = 7000;
  294. }
  295. ret = max30102_get_current_idx(val, &reg);
  296. if (ret) {
  297. dev_err(dev, "invalid green LED current setting %d\n",
  298. val);
  299. return ret;
  300. }
  301. ret = regmap_write(data->regmap, MAX30105_REG_GREEN_LED_CONFIG,
  302. reg);
  303. if (ret)
  304. return ret;
  305. }
  306. ret = device_property_read_u32(dev, "maxim,ir-led-current-microamp", &val);
  307. if (ret) {
  308. dev_info(dev, "no ir-led-current-microamp set\n");
  309. /* Default to 7 mA IR LED */
  310. val = 7000;
  311. }
  312. ret = max30102_get_current_idx(val, &reg);
  313. if (ret) {
  314. dev_err(dev, "invalid IR LED current setting %d\n", val);
  315. return ret;
  316. }
  317. return regmap_write(data->regmap, MAX30102_REG_IR_LED_CONFIG, reg);
  318. }
  319. static int max30102_chip_init(struct max30102_data *data)
  320. {
  321. int ret;
  322. /* setup LED current settings */
  323. ret = max30102_led_init(data);
  324. if (ret)
  325. return ret;
  326. /* configure 18-bit HR + SpO2 readings at 400Hz */
  327. ret = regmap_write(data->regmap, MAX30102_REG_SPO2_CONFIG,
  328. (MAX30102_REG_SPO2_CONFIG_ADC_4096_STEPS
  329. << MAX30102_REG_SPO2_CONFIG_ADC_MASK_SHIFT) |
  330. (MAX30102_REG_SPO2_CONFIG_SR_400HZ
  331. << MAX30102_REG_SPO2_CONFIG_SR_MASK_SHIFT) |
  332. MAX30102_REG_SPO2_CONFIG_PULSE_411_US);
  333. if (ret)
  334. return ret;
  335. /* average 4 samples + generate FIFO interrupt */
  336. ret = regmap_write(data->regmap, MAX30102_REG_FIFO_CONFIG,
  337. (MAX30102_REG_FIFO_CONFIG_AVG_4SAMPLES
  338. << MAX30102_REG_FIFO_CONFIG_AVG_SHIFT) |
  339. MAX30102_REG_FIFO_CONFIG_AFULL);
  340. if (ret)
  341. return ret;
  342. /* enable FIFO interrupt */
  343. return regmap_update_bits(data->regmap, MAX30102_REG_INT_ENABLE,
  344. MAX30102_REG_INT_ENABLE_MASK,
  345. MAX30102_REG_INT_ENABLE_FIFO_EN);
  346. }
  347. static int max30102_read_temp(struct max30102_data *data, int *val)
  348. {
  349. int ret;
  350. unsigned int reg;
  351. ret = regmap_read(data->regmap, MAX30102_REG_TEMP_INTEGER, &reg);
  352. if (ret < 0)
  353. return ret;
  354. *val = reg << 4;
  355. ret = regmap_read(data->regmap, MAX30102_REG_TEMP_FRACTION, &reg);
  356. if (ret < 0)
  357. return ret;
  358. *val |= reg & 0xf;
  359. *val = sign_extend32(*val, 11);
  360. return 0;
  361. }
  362. static int max30102_get_temp(struct max30102_data *data, int *val, bool en)
  363. {
  364. int ret;
  365. if (en) {
  366. ret = max30102_set_power(data, true);
  367. if (ret)
  368. return ret;
  369. }
  370. /* start acquisition */
  371. ret = regmap_set_bits(data->regmap, MAX30102_REG_TEMP_CONFIG,
  372. MAX30102_REG_TEMP_CONFIG_TEMP_EN);
  373. if (ret)
  374. goto out;
  375. msleep(35);
  376. ret = max30102_read_temp(data, val);
  377. out:
  378. if (en)
  379. max30102_set_power(data, false);
  380. return ret;
  381. }
  382. static int max30102_read_raw(struct iio_dev *indio_dev,
  383. struct iio_chan_spec const *chan,
  384. int *val, int *val2, long mask)
  385. {
  386. struct max30102_data *data = iio_priv(indio_dev);
  387. int ret = -EINVAL;
  388. switch (mask) {
  389. case IIO_CHAN_INFO_RAW:
  390. /*
  391. * Temperature reading can only be acquired when not in
  392. * shutdown; leave shutdown briefly when buffer not running
  393. */
  394. any_mode_retry:
  395. if (iio_device_claim_buffer_mode(indio_dev)) {
  396. /*
  397. * This one is a *bit* hacky. If we cannot claim buffer
  398. * mode, then try direct mode so that we make sure
  399. * things cannot concurrently change. And we just keep
  400. * trying until we get one of the modes...
  401. */
  402. if (iio_device_claim_direct_mode(indio_dev))
  403. goto any_mode_retry;
  404. ret = max30102_get_temp(data, val, true);
  405. iio_device_release_direct_mode(indio_dev);
  406. } else {
  407. ret = max30102_get_temp(data, val, false);
  408. iio_device_release_buffer_mode(indio_dev);
  409. }
  410. if (ret)
  411. return ret;
  412. ret = IIO_VAL_INT;
  413. break;
  414. case IIO_CHAN_INFO_SCALE:
  415. *val = 1000; /* 62.5 */
  416. *val2 = 16;
  417. ret = IIO_VAL_FRACTIONAL;
  418. break;
  419. }
  420. return ret;
  421. }
  422. static const struct iio_info max30102_info = {
  423. .read_raw = max30102_read_raw,
  424. };
  425. static int max30102_probe(struct i2c_client *client)
  426. {
  427. const struct i2c_device_id *id = i2c_client_get_device_id(client);
  428. struct max30102_data *data;
  429. struct iio_dev *indio_dev;
  430. int ret;
  431. unsigned int reg;
  432. indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
  433. if (!indio_dev)
  434. return -ENOMEM;
  435. indio_dev->name = MAX30102_DRV_NAME;
  436. indio_dev->info = &max30102_info;
  437. indio_dev->modes = INDIO_DIRECT_MODE;
  438. data = iio_priv(indio_dev);
  439. data->indio_dev = indio_dev;
  440. data->client = client;
  441. data->chip_id = id->driver_data;
  442. mutex_init(&data->lock);
  443. i2c_set_clientdata(client, indio_dev);
  444. switch (data->chip_id) {
  445. case max30105:
  446. indio_dev->channels = max30105_channels;
  447. indio_dev->num_channels = ARRAY_SIZE(max30105_channels);
  448. indio_dev->available_scan_masks = max30105_scan_masks;
  449. break;
  450. case max30102:
  451. indio_dev->channels = max30102_channels;
  452. indio_dev->num_channels = ARRAY_SIZE(max30102_channels);
  453. indio_dev->available_scan_masks = max30102_scan_masks;
  454. break;
  455. default:
  456. return -ENODEV;
  457. }
  458. ret = devm_iio_kfifo_buffer_setup(&client->dev, indio_dev,
  459. &max30102_buffer_setup_ops);
  460. if (ret)
  461. return ret;
  462. data->regmap = devm_regmap_init_i2c(client, &max30102_regmap_config);
  463. if (IS_ERR(data->regmap)) {
  464. dev_err(&client->dev, "regmap initialization failed\n");
  465. return PTR_ERR(data->regmap);
  466. }
  467. /* check part ID */
  468. ret = regmap_read(data->regmap, MAX30102_REG_PART_ID, &reg);
  469. if (ret)
  470. return ret;
  471. if (reg != MAX30102_PART_NUMBER)
  472. return -ENODEV;
  473. /* show revision ID */
  474. ret = regmap_read(data->regmap, MAX30102_REG_REV_ID, &reg);
  475. if (ret)
  476. return ret;
  477. dev_dbg(&client->dev, "max3010x revision %02x\n", reg);
  478. /* clear mode setting, chip shutdown */
  479. ret = max30102_set_powermode(data, MAX30102_REG_MODE_CONFIG_MODE_NONE,
  480. false);
  481. if (ret)
  482. return ret;
  483. ret = max30102_chip_init(data);
  484. if (ret)
  485. return ret;
  486. if (client->irq <= 0) {
  487. dev_err(&client->dev, "no valid irq defined\n");
  488. return -EINVAL;
  489. }
  490. ret = devm_request_threaded_irq(&client->dev, client->irq,
  491. NULL, max30102_interrupt_handler,
  492. IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
  493. "max30102_irq", indio_dev);
  494. if (ret) {
  495. dev_err(&client->dev, "request irq (%d) failed\n", client->irq);
  496. return ret;
  497. }
  498. return iio_device_register(indio_dev);
  499. }
  500. static void max30102_remove(struct i2c_client *client)
  501. {
  502. struct iio_dev *indio_dev = i2c_get_clientdata(client);
  503. struct max30102_data *data = iio_priv(indio_dev);
  504. iio_device_unregister(indio_dev);
  505. max30102_set_power(data, false);
  506. }
  507. static const struct i2c_device_id max30102_id[] = {
  508. { "max30101", max30105 },
  509. { "max30102", max30102 },
  510. { "max30105", max30105 },
  511. {}
  512. };
  513. MODULE_DEVICE_TABLE(i2c, max30102_id);
  514. static const struct of_device_id max30102_dt_ids[] = {
  515. { .compatible = "maxim,max30101" },
  516. { .compatible = "maxim,max30102" },
  517. { .compatible = "maxim,max30105" },
  518. { }
  519. };
  520. MODULE_DEVICE_TABLE(of, max30102_dt_ids);
  521. static struct i2c_driver max30102_driver = {
  522. .driver = {
  523. .name = MAX30102_DRV_NAME,
  524. .of_match_table = max30102_dt_ids,
  525. },
  526. .probe = max30102_probe,
  527. .remove = max30102_remove,
  528. .id_table = max30102_id,
  529. };
  530. module_i2c_driver(max30102_driver);
  531. MODULE_AUTHOR("Matt Ranostay <matt.ranostay@konsulko.com>");
  532. MODULE_DESCRIPTION("MAX30102 heart rate/pulse oximeter and MAX30105 particle sensor driver");
  533. MODULE_LICENSE("GPL");