ds90ub913.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Driver for the Texas Instruments DS90UB913 video serializer
  4. *
  5. * Based on a driver from Luca Ceresoli <luca@lucaceresoli.net>
  6. *
  7. * Copyright (c) 2019 Luca Ceresoli <luca@lucaceresoli.net>
  8. * Copyright (c) 2023 Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
  9. */
  10. #include <linux/bitfield.h>
  11. #include <linux/clk-provider.h>
  12. #include <linux/clk.h>
  13. #include <linux/delay.h>
  14. #include <linux/fwnode.h>
  15. #include <linux/gpio/driver.h>
  16. #include <linux/i2c-atr.h>
  17. #include <linux/i2c.h>
  18. #include <linux/kernel.h>
  19. #include <linux/module.h>
  20. #include <linux/property.h>
  21. #include <linux/regmap.h>
  22. #include <media/i2c/ds90ub9xx.h>
  23. #include <media/v4l2-fwnode.h>
  24. #include <media/v4l2-mediabus.h>
  25. #include <media/v4l2-subdev.h>
  26. #define UB913_PAD_SINK 0
  27. #define UB913_PAD_SOURCE 1
  28. /*
  29. * UB913 has 4 gpios, but gpios 3 and 4 are reserved for external oscillator
  30. * mode. Thus we only support 2 gpios for now.
  31. */
  32. #define UB913_NUM_GPIOS 2
  33. #define UB913_REG_RESET_CTL 0x01
  34. #define UB913_REG_RESET_CTL_DIGITAL_RESET_1 BIT(1)
  35. #define UB913_REG_RESET_CTL_DIGITAL_RESET_0 BIT(0)
  36. #define UB913_REG_GENERAL_CFG 0x03
  37. #define UB913_REG_GENERAL_CFG_CRC_ERR_RESET BIT(5)
  38. #define UB913_REG_GENERAL_CFG_PCLK_RISING BIT(0)
  39. #define UB913_REG_MODE_SEL 0x05
  40. #define UB913_REG_MODE_SEL_MODE_OVERRIDE BIT(5)
  41. #define UB913_REG_MODE_SEL_MODE_UP_TO_DATE BIT(4)
  42. #define UB913_REG_MODE_SEL_MODE_MASK GENMASK(3, 0)
  43. #define UB913_REG_CRC_ERRORS_LSB 0x0a
  44. #define UB913_REG_CRC_ERRORS_MSB 0x0b
  45. #define UB913_REG_GENERAL_STATUS 0x0c
  46. #define UB913_REG_GPIO_CFG(n) (0x0d + (n))
  47. #define UB913_REG_GPIO_CFG_ENABLE(n) BIT(0 + (n) * 4)
  48. #define UB913_REG_GPIO_CFG_DIR_INPUT(n) BIT(1 + (n) * 4)
  49. #define UB913_REG_GPIO_CFG_REMOTE_EN(n) BIT(2 + (n) * 4)
  50. #define UB913_REG_GPIO_CFG_OUT_VAL(n) BIT(3 + (n) * 4)
  51. #define UB913_REG_GPIO_CFG_MASK(n) (0xf << ((n) * 4))
  52. #define UB913_REG_SCL_HIGH_TIME 0x11
  53. #define UB913_REG_SCL_LOW_TIME 0x12
  54. #define UB913_REG_PLL_OVR 0x35
  55. struct ub913_data {
  56. struct i2c_client *client;
  57. struct regmap *regmap;
  58. struct clk *clkin;
  59. struct gpio_chip gpio_chip;
  60. struct v4l2_subdev sd;
  61. struct media_pad pads[2];
  62. struct v4l2_async_notifier notifier;
  63. struct v4l2_subdev *source_sd;
  64. u16 source_sd_pad;
  65. u64 enabled_source_streams;
  66. struct clk_hw *clkout_clk_hw;
  67. struct ds90ub9xx_platform_data *plat_data;
  68. bool pclk_polarity_rising;
  69. };
  70. static inline struct ub913_data *sd_to_ub913(struct v4l2_subdev *sd)
  71. {
  72. return container_of(sd, struct ub913_data, sd);
  73. }
  74. struct ub913_format_info {
  75. u32 incode;
  76. u32 outcode;
  77. };
  78. static const struct ub913_format_info ub913_formats[] = {
  79. /* Only RAW10 with 8-bit payload is supported at the moment */
  80. { .incode = MEDIA_BUS_FMT_YUYV8_2X8, .outcode = MEDIA_BUS_FMT_YUYV8_1X16 },
  81. { .incode = MEDIA_BUS_FMT_UYVY8_2X8, .outcode = MEDIA_BUS_FMT_UYVY8_1X16 },
  82. { .incode = MEDIA_BUS_FMT_VYUY8_2X8, .outcode = MEDIA_BUS_FMT_VYUY8_1X16 },
  83. { .incode = MEDIA_BUS_FMT_YVYU8_2X8, .outcode = MEDIA_BUS_FMT_YVYU8_1X16 },
  84. };
  85. static const struct ub913_format_info *ub913_find_format(u32 incode)
  86. {
  87. unsigned int i;
  88. for (i = 0; i < ARRAY_SIZE(ub913_formats); i++) {
  89. if (ub913_formats[i].incode == incode)
  90. return &ub913_formats[i];
  91. }
  92. return NULL;
  93. }
  94. static int ub913_read(const struct ub913_data *priv, u8 reg, u8 *val)
  95. {
  96. unsigned int v;
  97. int ret;
  98. ret = regmap_read(priv->regmap, reg, &v);
  99. if (ret < 0) {
  100. dev_err(&priv->client->dev,
  101. "Cannot read register 0x%02x: %d!\n", reg, ret);
  102. return ret;
  103. }
  104. *val = v;
  105. return 0;
  106. }
  107. static int ub913_write(const struct ub913_data *priv, u8 reg, u8 val)
  108. {
  109. int ret;
  110. ret = regmap_write(priv->regmap, reg, val);
  111. if (ret < 0)
  112. dev_err(&priv->client->dev,
  113. "Cannot write register 0x%02x: %d!\n", reg, ret);
  114. return ret;
  115. }
  116. static int ub913_update_bits(const struct ub913_data *priv, u8 reg, u8 mask,
  117. u8 val)
  118. {
  119. int ret;
  120. ret = regmap_update_bits(priv->regmap, reg, mask, val);
  121. if (ret < 0)
  122. dev_err(&priv->client->dev,
  123. "Cannot update register 0x%02x %d!\n", reg, ret);
  124. return ret;
  125. }
  126. /*
  127. * GPIO chip
  128. */
  129. static int ub913_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
  130. {
  131. return GPIO_LINE_DIRECTION_OUT;
  132. }
  133. static int ub913_gpio_direction_out(struct gpio_chip *gc, unsigned int offset,
  134. int value)
  135. {
  136. struct ub913_data *priv = gpiochip_get_data(gc);
  137. unsigned int reg_idx = offset / 2;
  138. unsigned int field_idx = offset % 2;
  139. return regmap_update_bits(priv->regmap, UB913_REG_GPIO_CFG(reg_idx),
  140. UB913_REG_GPIO_CFG_MASK(field_idx),
  141. UB913_REG_GPIO_CFG_ENABLE(field_idx) |
  142. (value ? UB913_REG_GPIO_CFG_OUT_VAL(field_idx) :
  143. 0));
  144. }
  145. static void ub913_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
  146. {
  147. ub913_gpio_direction_out(gc, offset, value);
  148. }
  149. static int ub913_gpio_of_xlate(struct gpio_chip *gc,
  150. const struct of_phandle_args *gpiospec,
  151. u32 *flags)
  152. {
  153. if (flags)
  154. *flags = gpiospec->args[1];
  155. return gpiospec->args[0];
  156. }
  157. static int ub913_gpiochip_probe(struct ub913_data *priv)
  158. {
  159. struct device *dev = &priv->client->dev;
  160. struct gpio_chip *gc = &priv->gpio_chip;
  161. int ret;
  162. /* Initialize GPIOs 0 and 1 to local control, tri-state */
  163. ub913_write(priv, UB913_REG_GPIO_CFG(0), 0);
  164. gc->label = dev_name(dev);
  165. gc->parent = dev;
  166. gc->owner = THIS_MODULE;
  167. gc->base = -1;
  168. gc->can_sleep = true;
  169. gc->ngpio = UB913_NUM_GPIOS;
  170. gc->get_direction = ub913_gpio_get_direction;
  171. gc->direction_output = ub913_gpio_direction_out;
  172. gc->set = ub913_gpio_set;
  173. gc->of_xlate = ub913_gpio_of_xlate;
  174. gc->of_gpio_n_cells = 2;
  175. ret = gpiochip_add_data(gc, priv);
  176. if (ret) {
  177. dev_err(dev, "Failed to add GPIOs: %d\n", ret);
  178. return ret;
  179. }
  180. return 0;
  181. }
  182. static void ub913_gpiochip_remove(struct ub913_data *priv)
  183. {
  184. gpiochip_remove(&priv->gpio_chip);
  185. }
  186. static const struct regmap_config ub913_regmap_config = {
  187. .name = "ds90ub913",
  188. .reg_bits = 8,
  189. .val_bits = 8,
  190. .reg_format_endian = REGMAP_ENDIAN_DEFAULT,
  191. .val_format_endian = REGMAP_ENDIAN_DEFAULT,
  192. };
  193. /*
  194. * V4L2
  195. */
  196. static int ub913_enable_streams(struct v4l2_subdev *sd,
  197. struct v4l2_subdev_state *state, u32 pad,
  198. u64 streams_mask)
  199. {
  200. struct ub913_data *priv = sd_to_ub913(sd);
  201. u64 sink_streams;
  202. int ret;
  203. sink_streams = v4l2_subdev_state_xlate_streams(state, UB913_PAD_SOURCE,
  204. UB913_PAD_SINK,
  205. &streams_mask);
  206. ret = v4l2_subdev_enable_streams(priv->source_sd, priv->source_sd_pad,
  207. sink_streams);
  208. if (ret)
  209. return ret;
  210. priv->enabled_source_streams |= streams_mask;
  211. return 0;
  212. }
  213. static int ub913_disable_streams(struct v4l2_subdev *sd,
  214. struct v4l2_subdev_state *state, u32 pad,
  215. u64 streams_mask)
  216. {
  217. struct ub913_data *priv = sd_to_ub913(sd);
  218. u64 sink_streams;
  219. int ret;
  220. sink_streams = v4l2_subdev_state_xlate_streams(state, UB913_PAD_SOURCE,
  221. UB913_PAD_SINK,
  222. &streams_mask);
  223. ret = v4l2_subdev_disable_streams(priv->source_sd, priv->source_sd_pad,
  224. sink_streams);
  225. if (ret)
  226. return ret;
  227. priv->enabled_source_streams &= ~streams_mask;
  228. return 0;
  229. }
  230. static int _ub913_set_routing(struct v4l2_subdev *sd,
  231. struct v4l2_subdev_state *state,
  232. struct v4l2_subdev_krouting *routing)
  233. {
  234. static const struct v4l2_mbus_framefmt in_format = {
  235. .width = 640,
  236. .height = 480,
  237. .code = MEDIA_BUS_FMT_UYVY8_2X8,
  238. .field = V4L2_FIELD_NONE,
  239. .colorspace = V4L2_COLORSPACE_SRGB,
  240. .ycbcr_enc = V4L2_YCBCR_ENC_601,
  241. .quantization = V4L2_QUANTIZATION_LIM_RANGE,
  242. .xfer_func = V4L2_XFER_FUNC_SRGB,
  243. };
  244. static const struct v4l2_mbus_framefmt out_format = {
  245. .width = 640,
  246. .height = 480,
  247. .code = MEDIA_BUS_FMT_UYVY8_1X16,
  248. .field = V4L2_FIELD_NONE,
  249. .colorspace = V4L2_COLORSPACE_SRGB,
  250. .ycbcr_enc = V4L2_YCBCR_ENC_601,
  251. .quantization = V4L2_QUANTIZATION_LIM_RANGE,
  252. .xfer_func = V4L2_XFER_FUNC_SRGB,
  253. };
  254. struct v4l2_subdev_stream_configs *stream_configs;
  255. unsigned int i;
  256. int ret;
  257. /*
  258. * Note: we can only support up to V4L2_FRAME_DESC_ENTRY_MAX, until
  259. * frame desc is made dynamically allocated.
  260. */
  261. if (routing->num_routes > V4L2_FRAME_DESC_ENTRY_MAX)
  262. return -EINVAL;
  263. ret = v4l2_subdev_routing_validate(sd, routing,
  264. V4L2_SUBDEV_ROUTING_ONLY_1_TO_1);
  265. if (ret)
  266. return ret;
  267. ret = v4l2_subdev_set_routing(sd, state, routing);
  268. if (ret)
  269. return ret;
  270. stream_configs = &state->stream_configs;
  271. for (i = 0; i < stream_configs->num_configs; i++) {
  272. if (stream_configs->configs[i].pad == UB913_PAD_SINK)
  273. stream_configs->configs[i].fmt = in_format;
  274. else
  275. stream_configs->configs[i].fmt = out_format;
  276. }
  277. return 0;
  278. }
  279. static int ub913_set_routing(struct v4l2_subdev *sd,
  280. struct v4l2_subdev_state *state,
  281. enum v4l2_subdev_format_whence which,
  282. struct v4l2_subdev_krouting *routing)
  283. {
  284. struct ub913_data *priv = sd_to_ub913(sd);
  285. if (which == V4L2_SUBDEV_FORMAT_ACTIVE && priv->enabled_source_streams)
  286. return -EBUSY;
  287. return _ub913_set_routing(sd, state, routing);
  288. }
  289. static int ub913_get_frame_desc(struct v4l2_subdev *sd, unsigned int pad,
  290. struct v4l2_mbus_frame_desc *fd)
  291. {
  292. struct ub913_data *priv = sd_to_ub913(sd);
  293. const struct v4l2_subdev_krouting *routing;
  294. struct v4l2_mbus_frame_desc source_fd;
  295. struct v4l2_subdev_route *route;
  296. struct v4l2_subdev_state *state;
  297. int ret;
  298. if (pad != UB913_PAD_SOURCE)
  299. return -EINVAL;
  300. ret = v4l2_subdev_call(priv->source_sd, pad, get_frame_desc,
  301. priv->source_sd_pad, &source_fd);
  302. if (ret)
  303. return ret;
  304. fd->type = V4L2_MBUS_FRAME_DESC_TYPE_PARALLEL;
  305. state = v4l2_subdev_lock_and_get_active_state(sd);
  306. routing = &state->routing;
  307. for_each_active_route(routing, route) {
  308. unsigned int i;
  309. if (route->source_pad != pad)
  310. continue;
  311. for (i = 0; i < source_fd.num_entries; i++) {
  312. if (source_fd.entry[i].stream == route->sink_stream)
  313. break;
  314. }
  315. if (i == source_fd.num_entries) {
  316. dev_err(&priv->client->dev,
  317. "Failed to find stream from source frame desc\n");
  318. ret = -EPIPE;
  319. goto out_unlock;
  320. }
  321. fd->entry[fd->num_entries].stream = route->source_stream;
  322. fd->entry[fd->num_entries].flags = source_fd.entry[i].flags;
  323. fd->entry[fd->num_entries].length = source_fd.entry[i].length;
  324. fd->entry[fd->num_entries].pixelcode =
  325. source_fd.entry[i].pixelcode;
  326. fd->num_entries++;
  327. }
  328. out_unlock:
  329. v4l2_subdev_unlock_state(state);
  330. return ret;
  331. }
  332. static int ub913_set_fmt(struct v4l2_subdev *sd,
  333. struct v4l2_subdev_state *state,
  334. struct v4l2_subdev_format *format)
  335. {
  336. struct ub913_data *priv = sd_to_ub913(sd);
  337. struct v4l2_mbus_framefmt *fmt;
  338. const struct ub913_format_info *finfo;
  339. if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE &&
  340. priv->enabled_source_streams)
  341. return -EBUSY;
  342. /* Source format is fully defined by the sink format, so not settable */
  343. if (format->pad == UB913_PAD_SOURCE)
  344. return v4l2_subdev_get_fmt(sd, state, format);
  345. finfo = ub913_find_format(format->format.code);
  346. if (!finfo) {
  347. finfo = &ub913_formats[0];
  348. format->format.code = finfo->incode;
  349. }
  350. /* Set sink format */
  351. fmt = v4l2_subdev_state_get_format(state, format->pad, format->stream);
  352. if (!fmt)
  353. return -EINVAL;
  354. *fmt = format->format;
  355. /* Propagate to source format, and adjust the mbus code */
  356. fmt = v4l2_subdev_state_get_opposite_stream_format(state, format->pad,
  357. format->stream);
  358. if (!fmt)
  359. return -EINVAL;
  360. *fmt = format->format;
  361. fmt->code = finfo->outcode;
  362. return 0;
  363. }
  364. static int ub913_init_state(struct v4l2_subdev *sd,
  365. struct v4l2_subdev_state *state)
  366. {
  367. struct v4l2_subdev_route routes[] = {
  368. {
  369. .sink_pad = UB913_PAD_SINK,
  370. .sink_stream = 0,
  371. .source_pad = UB913_PAD_SOURCE,
  372. .source_stream = 0,
  373. .flags = V4L2_SUBDEV_ROUTE_FL_ACTIVE,
  374. },
  375. };
  376. struct v4l2_subdev_krouting routing = {
  377. .num_routes = ARRAY_SIZE(routes),
  378. .routes = routes,
  379. };
  380. return _ub913_set_routing(sd, state, &routing);
  381. }
  382. static int ub913_log_status(struct v4l2_subdev *sd)
  383. {
  384. struct ub913_data *priv = sd_to_ub913(sd);
  385. struct device *dev = &priv->client->dev;
  386. u8 v = 0, v1 = 0, v2 = 0;
  387. ub913_read(priv, UB913_REG_MODE_SEL, &v);
  388. dev_info(dev, "MODE_SEL %#02x\n", v);
  389. ub913_read(priv, UB913_REG_CRC_ERRORS_LSB, &v1);
  390. ub913_read(priv, UB913_REG_CRC_ERRORS_MSB, &v2);
  391. dev_info(dev, "CRC errors %u\n", v1 | (v2 << 8));
  392. /* clear CRC errors */
  393. ub913_read(priv, UB913_REG_GENERAL_CFG, &v);
  394. ub913_write(priv, UB913_REG_GENERAL_CFG,
  395. v | UB913_REG_GENERAL_CFG_CRC_ERR_RESET);
  396. ub913_write(priv, UB913_REG_GENERAL_CFG, v);
  397. ub913_read(priv, UB913_REG_GENERAL_STATUS, &v);
  398. dev_info(dev, "GENERAL_STATUS %#02x\n", v);
  399. ub913_read(priv, UB913_REG_PLL_OVR, &v);
  400. dev_info(dev, "PLL_OVR %#02x\n", v);
  401. return 0;
  402. }
  403. static const struct v4l2_subdev_core_ops ub913_subdev_core_ops = {
  404. .log_status = ub913_log_status,
  405. };
  406. static const struct v4l2_subdev_pad_ops ub913_pad_ops = {
  407. .enable_streams = ub913_enable_streams,
  408. .disable_streams = ub913_disable_streams,
  409. .set_routing = ub913_set_routing,
  410. .get_frame_desc = ub913_get_frame_desc,
  411. .get_fmt = v4l2_subdev_get_fmt,
  412. .set_fmt = ub913_set_fmt,
  413. };
  414. static const struct v4l2_subdev_ops ub913_subdev_ops = {
  415. .core = &ub913_subdev_core_ops,
  416. .pad = &ub913_pad_ops,
  417. };
  418. static const struct v4l2_subdev_internal_ops ub913_internal_ops = {
  419. .init_state = ub913_init_state,
  420. };
  421. static const struct media_entity_operations ub913_entity_ops = {
  422. .link_validate = v4l2_subdev_link_validate,
  423. };
  424. static int ub913_notify_bound(struct v4l2_async_notifier *notifier,
  425. struct v4l2_subdev *source_subdev,
  426. struct v4l2_async_connection *asd)
  427. {
  428. struct ub913_data *priv = sd_to_ub913(notifier->sd);
  429. struct device *dev = &priv->client->dev;
  430. int ret;
  431. ret = media_entity_get_fwnode_pad(&source_subdev->entity,
  432. source_subdev->fwnode,
  433. MEDIA_PAD_FL_SOURCE);
  434. if (ret < 0) {
  435. dev_err(dev, "Failed to find pad for %s\n",
  436. source_subdev->name);
  437. return ret;
  438. }
  439. priv->source_sd = source_subdev;
  440. priv->source_sd_pad = ret;
  441. ret = media_create_pad_link(&source_subdev->entity, priv->source_sd_pad,
  442. &priv->sd.entity, UB913_PAD_SINK,
  443. MEDIA_LNK_FL_ENABLED |
  444. MEDIA_LNK_FL_IMMUTABLE);
  445. if (ret) {
  446. dev_err(dev, "Unable to link %s:%u -> %s:0\n",
  447. source_subdev->name, priv->source_sd_pad,
  448. priv->sd.name);
  449. return ret;
  450. }
  451. return 0;
  452. }
  453. static const struct v4l2_async_notifier_operations ub913_notify_ops = {
  454. .bound = ub913_notify_bound,
  455. };
  456. static int ub913_v4l2_notifier_register(struct ub913_data *priv)
  457. {
  458. struct device *dev = &priv->client->dev;
  459. struct v4l2_async_connection *asd;
  460. struct fwnode_handle *ep_fwnode;
  461. int ret;
  462. ep_fwnode = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev),
  463. UB913_PAD_SINK, 0, 0);
  464. if (!ep_fwnode) {
  465. dev_err(dev, "No graph endpoint\n");
  466. return -ENODEV;
  467. }
  468. v4l2_async_subdev_nf_init(&priv->notifier, &priv->sd);
  469. asd = v4l2_async_nf_add_fwnode_remote(&priv->notifier, ep_fwnode,
  470. struct v4l2_async_connection);
  471. fwnode_handle_put(ep_fwnode);
  472. if (IS_ERR(asd)) {
  473. dev_err(dev, "Failed to add subdev: %ld", PTR_ERR(asd));
  474. v4l2_async_nf_cleanup(&priv->notifier);
  475. return PTR_ERR(asd);
  476. }
  477. priv->notifier.ops = &ub913_notify_ops;
  478. ret = v4l2_async_nf_register(&priv->notifier);
  479. if (ret) {
  480. dev_err(dev, "Failed to register subdev_notifier");
  481. v4l2_async_nf_cleanup(&priv->notifier);
  482. return ret;
  483. }
  484. return 0;
  485. }
  486. static void ub913_v4l2_nf_unregister(struct ub913_data *priv)
  487. {
  488. v4l2_async_nf_unregister(&priv->notifier);
  489. v4l2_async_nf_cleanup(&priv->notifier);
  490. }
  491. static int ub913_register_clkout(struct ub913_data *priv)
  492. {
  493. struct device *dev = &priv->client->dev;
  494. const char *name;
  495. int ret;
  496. name = kasprintf(GFP_KERNEL, "ds90ub913.%s.clk_out", dev_name(dev));
  497. if (!name)
  498. return -ENOMEM;
  499. priv->clkout_clk_hw = devm_clk_hw_register_fixed_factor(dev, name,
  500. __clk_get_name(priv->clkin), 0, 1, 2);
  501. kfree(name);
  502. if (IS_ERR(priv->clkout_clk_hw))
  503. return dev_err_probe(dev, PTR_ERR(priv->clkout_clk_hw),
  504. "Cannot register clkout hw\n");
  505. ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
  506. priv->clkout_clk_hw);
  507. if (ret)
  508. return dev_err_probe(dev, ret,
  509. "Cannot add OF clock provider\n");
  510. return 0;
  511. }
  512. static int ub913_i2c_master_init(struct ub913_data *priv)
  513. {
  514. /* i2c fast mode */
  515. u32 scl_high = 600 + 300; /* high period + rise time, ns */
  516. u32 scl_low = 1300 + 300; /* low period + fall time, ns */
  517. unsigned long ref;
  518. int ret;
  519. ref = clk_get_rate(priv->clkin) / 2;
  520. scl_high = div64_u64((u64)scl_high * ref, 1000000000);
  521. scl_low = div64_u64((u64)scl_low * ref, 1000000000);
  522. ret = ub913_write(priv, UB913_REG_SCL_HIGH_TIME, scl_high);
  523. if (ret)
  524. return ret;
  525. ret = ub913_write(priv, UB913_REG_SCL_LOW_TIME, scl_low);
  526. if (ret)
  527. return ret;
  528. return 0;
  529. }
  530. static int ub913_add_i2c_adapter(struct ub913_data *priv)
  531. {
  532. struct device *dev = &priv->client->dev;
  533. struct fwnode_handle *i2c_handle;
  534. int ret;
  535. i2c_handle = device_get_named_child_node(dev, "i2c");
  536. if (!i2c_handle)
  537. return 0;
  538. ret = i2c_atr_add_adapter(priv->plat_data->atr, priv->plat_data->port,
  539. dev, i2c_handle);
  540. fwnode_handle_put(i2c_handle);
  541. if (ret)
  542. return ret;
  543. return 0;
  544. }
  545. static int ub913_parse_dt(struct ub913_data *priv)
  546. {
  547. struct device *dev = &priv->client->dev;
  548. struct v4l2_fwnode_endpoint vep = {
  549. .bus_type = V4L2_MBUS_PARALLEL,
  550. };
  551. struct fwnode_handle *ep_fwnode;
  552. int ret;
  553. ep_fwnode = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev),
  554. UB913_PAD_SINK, 0, 0);
  555. if (!ep_fwnode)
  556. return dev_err_probe(dev, -ENOENT, "No sink endpoint\n");
  557. ret = v4l2_fwnode_endpoint_parse(ep_fwnode, &vep);
  558. fwnode_handle_put(ep_fwnode);
  559. if (ret)
  560. return dev_err_probe(dev, ret,
  561. "failed to parse sink endpoint data\n");
  562. if (vep.bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
  563. priv->pclk_polarity_rising = true;
  564. else if (vep.bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
  565. priv->pclk_polarity_rising = false;
  566. else
  567. return dev_err_probe(dev, -EINVAL,
  568. "bad value for 'pclk-sample'\n");
  569. return 0;
  570. }
  571. static int ub913_hw_init(struct ub913_data *priv)
  572. {
  573. struct device *dev = &priv->client->dev;
  574. bool mode_override;
  575. u8 mode;
  576. int ret;
  577. u8 v;
  578. ret = ub913_read(priv, UB913_REG_MODE_SEL, &v);
  579. if (ret)
  580. return ret;
  581. if (!(v & UB913_REG_MODE_SEL_MODE_UP_TO_DATE))
  582. return dev_err_probe(dev, -ENODEV,
  583. "Mode value not stabilized\n");
  584. mode_override = v & UB913_REG_MODE_SEL_MODE_OVERRIDE;
  585. mode = v & UB913_REG_MODE_SEL_MODE_MASK;
  586. dev_dbg(dev, "mode from %s: %#x\n",
  587. mode_override ? "reg" : "deserializer", mode);
  588. ret = ub913_i2c_master_init(priv);
  589. if (ret)
  590. return dev_err_probe(dev, ret, "i2c master init failed\n");
  591. ret = ub913_update_bits(priv, UB913_REG_GENERAL_CFG,
  592. UB913_REG_GENERAL_CFG_PCLK_RISING,
  593. FIELD_PREP(UB913_REG_GENERAL_CFG_PCLK_RISING,
  594. priv->pclk_polarity_rising));
  595. if (ret)
  596. return ret;
  597. return 0;
  598. }
  599. static int ub913_subdev_init(struct ub913_data *priv)
  600. {
  601. struct device *dev = &priv->client->dev;
  602. int ret;
  603. v4l2_i2c_subdev_init(&priv->sd, priv->client, &ub913_subdev_ops);
  604. priv->sd.internal_ops = &ub913_internal_ops;
  605. priv->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_STREAMS;
  606. priv->sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
  607. priv->sd.entity.ops = &ub913_entity_ops;
  608. priv->pads[0].flags = MEDIA_PAD_FL_SINK;
  609. priv->pads[1].flags = MEDIA_PAD_FL_SOURCE;
  610. ret = media_entity_pads_init(&priv->sd.entity, 2, priv->pads);
  611. if (ret)
  612. return dev_err_probe(dev, ret, "Failed to init pads\n");
  613. ret = v4l2_subdev_init_finalize(&priv->sd);
  614. if (ret)
  615. goto err_entity_cleanup;
  616. ret = ub913_v4l2_notifier_register(priv);
  617. if (ret) {
  618. dev_err_probe(dev, ret,
  619. "v4l2 subdev notifier register failed\n");
  620. goto err_subdev_cleanup;
  621. }
  622. ret = v4l2_async_register_subdev(&priv->sd);
  623. if (ret) {
  624. dev_err_probe(dev, ret, "v4l2_async_register_subdev error\n");
  625. goto err_unreg_notif;
  626. }
  627. return 0;
  628. err_unreg_notif:
  629. ub913_v4l2_nf_unregister(priv);
  630. err_subdev_cleanup:
  631. v4l2_subdev_cleanup(&priv->sd);
  632. err_entity_cleanup:
  633. media_entity_cleanup(&priv->sd.entity);
  634. return ret;
  635. }
  636. static void ub913_subdev_uninit(struct ub913_data *priv)
  637. {
  638. v4l2_async_unregister_subdev(&priv->sd);
  639. ub913_v4l2_nf_unregister(priv);
  640. v4l2_subdev_cleanup(&priv->sd);
  641. media_entity_cleanup(&priv->sd.entity);
  642. }
  643. static int ub913_probe(struct i2c_client *client)
  644. {
  645. struct device *dev = &client->dev;
  646. struct ub913_data *priv;
  647. int ret;
  648. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  649. if (!priv)
  650. return -ENOMEM;
  651. priv->client = client;
  652. priv->plat_data = dev_get_platdata(&client->dev);
  653. if (!priv->plat_data)
  654. return dev_err_probe(dev, -ENODEV, "Platform data missing\n");
  655. priv->regmap = devm_regmap_init_i2c(client, &ub913_regmap_config);
  656. if (IS_ERR(priv->regmap))
  657. return dev_err_probe(dev, PTR_ERR(priv->regmap),
  658. "Failed to init regmap\n");
  659. /*
  660. * ub913 can also work without ext clock, but that is not supported by
  661. * the driver yet.
  662. */
  663. priv->clkin = devm_clk_get(dev, "clkin");
  664. if (IS_ERR(priv->clkin))
  665. return dev_err_probe(dev, PTR_ERR(priv->clkin),
  666. "Cannot get CLKIN\n");
  667. ret = ub913_parse_dt(priv);
  668. if (ret)
  669. return ret;
  670. ret = ub913_hw_init(priv);
  671. if (ret)
  672. return ret;
  673. ret = ub913_gpiochip_probe(priv);
  674. if (ret)
  675. return dev_err_probe(dev, ret, "Failed to init gpiochip\n");
  676. ret = ub913_register_clkout(priv);
  677. if (ret) {
  678. dev_err_probe(dev, ret, "Failed to register clkout\n");
  679. goto err_gpiochip_remove;
  680. }
  681. ret = ub913_subdev_init(priv);
  682. if (ret)
  683. goto err_gpiochip_remove;
  684. ret = ub913_add_i2c_adapter(priv);
  685. if (ret) {
  686. dev_err_probe(dev, ret, "failed to add remote i2c adapter\n");
  687. goto err_subdev_uninit;
  688. }
  689. return 0;
  690. err_subdev_uninit:
  691. ub913_subdev_uninit(priv);
  692. err_gpiochip_remove:
  693. ub913_gpiochip_remove(priv);
  694. return ret;
  695. }
  696. static void ub913_remove(struct i2c_client *client)
  697. {
  698. struct v4l2_subdev *sd = i2c_get_clientdata(client);
  699. struct ub913_data *priv = sd_to_ub913(sd);
  700. i2c_atr_del_adapter(priv->plat_data->atr, priv->plat_data->port);
  701. ub913_subdev_uninit(priv);
  702. ub913_gpiochip_remove(priv);
  703. }
  704. static const struct i2c_device_id ub913_id[] = {
  705. { "ds90ub913a-q1" },
  706. {}
  707. };
  708. MODULE_DEVICE_TABLE(i2c, ub913_id);
  709. static const struct of_device_id ub913_dt_ids[] = {
  710. { .compatible = "ti,ds90ub913a-q1" },
  711. {}
  712. };
  713. MODULE_DEVICE_TABLE(of, ub913_dt_ids);
  714. static struct i2c_driver ds90ub913_driver = {
  715. .probe = ub913_probe,
  716. .remove = ub913_remove,
  717. .id_table = ub913_id,
  718. .driver = {
  719. .name = "ds90ub913a",
  720. .of_match_table = ub913_dt_ids,
  721. },
  722. };
  723. module_i2c_driver(ds90ub913_driver);
  724. MODULE_LICENSE("GPL");
  725. MODULE_DESCRIPTION("Texas Instruments DS90UB913 FPD-Link III Serializer Driver");
  726. MODULE_AUTHOR("Luca Ceresoli <luca@lucaceresoli.net>");
  727. MODULE_AUTHOR("Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>");
  728. MODULE_IMPORT_NS(I2C_ATR);