mxs-ocotp.c 4.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195
  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Freescale MXS On-Chip OTP driver
  4. *
  5. * Copyright (C) 2015 Stefan Wahren <stefan.wahren@i2se.com>
  6. *
  7. * Based on the driver from Huang Shijie and Christoph G. Baumann
  8. */
  9. #include <linux/clk.h>
  10. #include <linux/delay.h>
  11. #include <linux/device.h>
  12. #include <linux/err.h>
  13. #include <linux/io.h>
  14. #include <linux/module.h>
  15. #include <linux/nvmem-provider.h>
  16. #include <linux/of.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/property.h>
  19. #include <linux/slab.h>
  20. #include <linux/stmp_device.h>
  21. /* OCOTP registers and bits */
  22. #define BM_OCOTP_CTRL_RD_BANK_OPEN BIT(12)
  23. #define BM_OCOTP_CTRL_ERROR BIT(9)
  24. #define BM_OCOTP_CTRL_BUSY BIT(8)
  25. #define OCOTP_TIMEOUT 10000
  26. #define OCOTP_DATA_OFFSET 0x20
  27. struct mxs_ocotp {
  28. struct clk *clk;
  29. void __iomem *base;
  30. struct nvmem_device *nvmem;
  31. };
  32. static int mxs_ocotp_wait(struct mxs_ocotp *otp)
  33. {
  34. int timeout = OCOTP_TIMEOUT;
  35. unsigned int status = 0;
  36. while (timeout--) {
  37. status = readl(otp->base);
  38. if (!(status & (BM_OCOTP_CTRL_BUSY | BM_OCOTP_CTRL_ERROR)))
  39. break;
  40. cpu_relax();
  41. }
  42. if (status & BM_OCOTP_CTRL_BUSY)
  43. return -EBUSY;
  44. else if (status & BM_OCOTP_CTRL_ERROR)
  45. return -EIO;
  46. return 0;
  47. }
  48. static int mxs_ocotp_read(void *context, unsigned int offset,
  49. void *val, size_t bytes)
  50. {
  51. struct mxs_ocotp *otp = context;
  52. u32 *buf = val;
  53. int ret;
  54. ret = clk_enable(otp->clk);
  55. if (ret)
  56. return ret;
  57. writel(BM_OCOTP_CTRL_ERROR, otp->base + STMP_OFFSET_REG_CLR);
  58. ret = mxs_ocotp_wait(otp);
  59. if (ret)
  60. goto disable_clk;
  61. /* open OCOTP banks for read */
  62. writel(BM_OCOTP_CTRL_RD_BANK_OPEN, otp->base + STMP_OFFSET_REG_SET);
  63. /* approximately wait 33 hclk cycles */
  64. udelay(1);
  65. ret = mxs_ocotp_wait(otp);
  66. if (ret)
  67. goto close_banks;
  68. while (bytes) {
  69. if ((offset < OCOTP_DATA_OFFSET) || (offset % 16)) {
  70. /* fill up non-data register */
  71. *buf++ = 0;
  72. } else {
  73. *buf++ = readl(otp->base + offset);
  74. }
  75. bytes -= 4;
  76. offset += 4;
  77. }
  78. close_banks:
  79. /* close banks for power saving */
  80. writel(BM_OCOTP_CTRL_RD_BANK_OPEN, otp->base + STMP_OFFSET_REG_CLR);
  81. disable_clk:
  82. clk_disable(otp->clk);
  83. return ret;
  84. }
  85. static struct nvmem_config ocotp_config = {
  86. .name = "mxs-ocotp",
  87. .stride = 16,
  88. .word_size = 4,
  89. .reg_read = mxs_ocotp_read,
  90. };
  91. struct mxs_data {
  92. int size;
  93. };
  94. static const struct mxs_data imx23_data = {
  95. .size = 0x220,
  96. };
  97. static const struct mxs_data imx28_data = {
  98. .size = 0x2a0,
  99. };
  100. static const struct of_device_id mxs_ocotp_match[] = {
  101. { .compatible = "fsl,imx23-ocotp", .data = &imx23_data },
  102. { .compatible = "fsl,imx28-ocotp", .data = &imx28_data },
  103. { /* sentinel */},
  104. };
  105. MODULE_DEVICE_TABLE(of, mxs_ocotp_match);
  106. static void mxs_ocotp_action(void *data)
  107. {
  108. clk_unprepare(data);
  109. }
  110. static int mxs_ocotp_probe(struct platform_device *pdev)
  111. {
  112. struct device *dev = &pdev->dev;
  113. const struct mxs_data *data;
  114. struct mxs_ocotp *otp;
  115. int ret;
  116. data = device_get_match_data(dev);
  117. if (!data)
  118. return -EINVAL;
  119. otp = devm_kzalloc(dev, sizeof(*otp), GFP_KERNEL);
  120. if (!otp)
  121. return -ENOMEM;
  122. otp->base = devm_platform_ioremap_resource(pdev, 0);
  123. if (IS_ERR(otp->base))
  124. return PTR_ERR(otp->base);
  125. otp->clk = devm_clk_get(&pdev->dev, NULL);
  126. if (IS_ERR(otp->clk))
  127. return PTR_ERR(otp->clk);
  128. ret = clk_prepare(otp->clk);
  129. if (ret < 0) {
  130. dev_err(dev, "failed to prepare clk: %d\n", ret);
  131. return ret;
  132. }
  133. ret = devm_add_action_or_reset(&pdev->dev, mxs_ocotp_action, otp->clk);
  134. if (ret)
  135. return ret;
  136. ocotp_config.size = data->size;
  137. ocotp_config.priv = otp;
  138. ocotp_config.dev = dev;
  139. otp->nvmem = devm_nvmem_register(dev, &ocotp_config);
  140. if (IS_ERR(otp->nvmem))
  141. return PTR_ERR(otp->nvmem);
  142. platform_set_drvdata(pdev, otp);
  143. return 0;
  144. }
  145. static struct platform_driver mxs_ocotp_driver = {
  146. .probe = mxs_ocotp_probe,
  147. .driver = {
  148. .name = "mxs-ocotp",
  149. .of_match_table = mxs_ocotp_match,
  150. },
  151. };
  152. module_platform_driver(mxs_ocotp_driver);
  153. MODULE_AUTHOR("Stefan Wahren <wahrenst@gmx.net");
  154. MODULE_DESCRIPTION("driver for OCOTP in i.MX23/i.MX28");
  155. MODULE_LICENSE("GPL v2");