reset-syscfg.c 4.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (C) 2013 STMicroelectronics Limited
  4. * Author: Stephen Gallimore <stephen.gallimore@st.com>
  5. *
  6. * Inspired by mach-imx/src.c
  7. */
  8. #include <linux/kernel.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/property.h>
  11. #include <linux/module.h>
  12. #include <linux/err.h>
  13. #include <linux/types.h>
  14. #include <linux/of.h>
  15. #include <linux/regmap.h>
  16. #include <linux/mfd/syscon.h>
  17. #include "reset-syscfg.h"
  18. /**
  19. * struct syscfg_reset_channel - Reset channel regmap configuration
  20. *
  21. * @reset: regmap field for the channel's reset bit.
  22. * @ack: regmap field for the channel's ack bit (optional).
  23. */
  24. struct syscfg_reset_channel {
  25. struct regmap_field *reset;
  26. struct regmap_field *ack;
  27. };
  28. /**
  29. * struct syscfg_reset_controller - A reset controller which groups together
  30. * a set of related reset bits, which may be located in different system
  31. * configuration registers.
  32. *
  33. * @rst: base reset controller structure.
  34. * @active_low: are the resets in this controller active low, i.e. clearing
  35. * the reset bit puts the hardware into reset.
  36. * @channels: An array of reset channels for this controller.
  37. */
  38. struct syscfg_reset_controller {
  39. struct reset_controller_dev rst;
  40. bool active_low;
  41. struct syscfg_reset_channel *channels;
  42. };
  43. #define to_syscfg_reset_controller(_rst) \
  44. container_of(_rst, struct syscfg_reset_controller, rst)
  45. static int syscfg_reset_program_hw(struct reset_controller_dev *rcdev,
  46. unsigned long idx, int assert)
  47. {
  48. struct syscfg_reset_controller *rst = to_syscfg_reset_controller(rcdev);
  49. const struct syscfg_reset_channel *ch;
  50. u32 ctrl_val = rst->active_low ? !assert : !!assert;
  51. int err;
  52. if (idx >= rcdev->nr_resets)
  53. return -EINVAL;
  54. ch = &rst->channels[idx];
  55. err = regmap_field_write(ch->reset, ctrl_val);
  56. if (err)
  57. return err;
  58. if (ch->ack) {
  59. u32 ack_val;
  60. err = regmap_field_read_poll_timeout(ch->ack, ack_val, (ack_val == ctrl_val),
  61. 100, USEC_PER_SEC);
  62. if (err)
  63. return err;
  64. }
  65. return 0;
  66. }
  67. static int syscfg_reset_assert(struct reset_controller_dev *rcdev,
  68. unsigned long idx)
  69. {
  70. return syscfg_reset_program_hw(rcdev, idx, true);
  71. }
  72. static int syscfg_reset_deassert(struct reset_controller_dev *rcdev,
  73. unsigned long idx)
  74. {
  75. return syscfg_reset_program_hw(rcdev, idx, false);
  76. }
  77. static int syscfg_reset_dev(struct reset_controller_dev *rcdev,
  78. unsigned long idx)
  79. {
  80. int err;
  81. err = syscfg_reset_assert(rcdev, idx);
  82. if (err)
  83. return err;
  84. return syscfg_reset_deassert(rcdev, idx);
  85. }
  86. static int syscfg_reset_status(struct reset_controller_dev *rcdev,
  87. unsigned long idx)
  88. {
  89. struct syscfg_reset_controller *rst = to_syscfg_reset_controller(rcdev);
  90. const struct syscfg_reset_channel *ch;
  91. u32 ret_val = 0;
  92. int err;
  93. if (idx >= rcdev->nr_resets)
  94. return -EINVAL;
  95. ch = &rst->channels[idx];
  96. if (ch->ack)
  97. err = regmap_field_read(ch->ack, &ret_val);
  98. else
  99. err = regmap_field_read(ch->reset, &ret_val);
  100. if (err)
  101. return err;
  102. return rst->active_low ? !ret_val : !!ret_val;
  103. }
  104. static const struct reset_control_ops syscfg_reset_ops = {
  105. .reset = syscfg_reset_dev,
  106. .assert = syscfg_reset_assert,
  107. .deassert = syscfg_reset_deassert,
  108. .status = syscfg_reset_status,
  109. };
  110. static int syscfg_reset_controller_register(struct device *dev,
  111. const struct syscfg_reset_controller_data *data)
  112. {
  113. struct syscfg_reset_controller *rc;
  114. int i, err;
  115. rc = devm_kzalloc(dev, sizeof(*rc), GFP_KERNEL);
  116. if (!rc)
  117. return -ENOMEM;
  118. rc->channels = devm_kcalloc(dev, data->nr_channels,
  119. sizeof(*rc->channels), GFP_KERNEL);
  120. if (!rc->channels)
  121. return -ENOMEM;
  122. rc->rst.ops = &syscfg_reset_ops;
  123. rc->rst.of_node = dev->of_node;
  124. rc->rst.nr_resets = data->nr_channels;
  125. rc->active_low = data->active_low;
  126. for (i = 0; i < data->nr_channels; i++) {
  127. struct regmap *map;
  128. struct regmap_field *f;
  129. const char *compatible = data->channels[i].compatible;
  130. map = syscon_regmap_lookup_by_compatible(compatible);
  131. if (IS_ERR(map))
  132. return PTR_ERR(map);
  133. f = devm_regmap_field_alloc(dev, map, data->channels[i].reset);
  134. if (IS_ERR(f))
  135. return PTR_ERR(f);
  136. rc->channels[i].reset = f;
  137. if (!data->wait_for_ack)
  138. continue;
  139. f = devm_regmap_field_alloc(dev, map, data->channels[i].ack);
  140. if (IS_ERR(f))
  141. return PTR_ERR(f);
  142. rc->channels[i].ack = f;
  143. }
  144. err = reset_controller_register(&rc->rst);
  145. if (!err)
  146. dev_info(dev, "registered\n");
  147. return err;
  148. }
  149. int syscfg_reset_probe(struct platform_device *pdev)
  150. {
  151. struct device *dev = pdev ? &pdev->dev : NULL;
  152. const void *data;
  153. if (!dev || !dev->driver)
  154. return -ENODEV;
  155. data = device_get_match_data(&pdev->dev);
  156. if (!data)
  157. return -EINVAL;
  158. return syscfg_reset_controller_register(dev, data);
  159. }