platform.c 20 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799
  1. // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
  2. /*
  3. * platform.c - DesignWare HS OTG Controller platform driver
  4. *
  5. * Copyright (C) Matthijs Kooijman <matthijs@stdin.nl>
  6. */
  7. #include <linux/kernel.h>
  8. #include <linux/module.h>
  9. #include <linux/slab.h>
  10. #include <linux/clk.h>
  11. #include <linux/device.h>
  12. #include <linux/dma-mapping.h>
  13. #include <linux/of.h>
  14. #include <linux/mutex.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/phy/phy.h>
  17. #include <linux/platform_data/s3c-hsotg.h>
  18. #include <linux/reset.h>
  19. #include <linux/of_gpio.h>
  20. #include <linux/usb/of.h>
  21. #include "core.h"
  22. #include "hcd.h"
  23. #include "debug.h"
  24. static const char dwc2_driver_name[] = "dwc2";
  25. /*
  26. * Check the dr_mode against the module configuration and hardware
  27. * capabilities.
  28. *
  29. * The hardware, module, and dr_mode, can each be set to host, device,
  30. * or otg. Check that all these values are compatible and adjust the
  31. * value of dr_mode if possible.
  32. *
  33. * actual
  34. * HW MOD dr_mode dr_mode
  35. * ------------------------------
  36. * HST HST any : HST
  37. * HST DEV any : ---
  38. * HST OTG any : HST
  39. *
  40. * DEV HST any : ---
  41. * DEV DEV any : DEV
  42. * DEV OTG any : DEV
  43. *
  44. * OTG HST any : HST
  45. * OTG DEV any : DEV
  46. * OTG OTG any : dr_mode
  47. */
  48. static int dwc2_get_dr_mode(struct dwc2_hsotg *hsotg)
  49. {
  50. enum usb_dr_mode mode;
  51. hsotg->dr_mode = usb_get_dr_mode(hsotg->dev);
  52. if (hsotg->dr_mode == USB_DR_MODE_UNKNOWN)
  53. hsotg->dr_mode = USB_DR_MODE_OTG;
  54. mode = hsotg->dr_mode;
  55. if (dwc2_hw_is_device(hsotg)) {
  56. if (IS_ENABLED(CONFIG_USB_DWC2_HOST)) {
  57. dev_err(hsotg->dev,
  58. "Controller does not support host mode.\n");
  59. return -EINVAL;
  60. }
  61. mode = USB_DR_MODE_PERIPHERAL;
  62. } else if (dwc2_hw_is_host(hsotg)) {
  63. if (IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL)) {
  64. dev_err(hsotg->dev,
  65. "Controller does not support device mode.\n");
  66. return -EINVAL;
  67. }
  68. mode = USB_DR_MODE_HOST;
  69. } else {
  70. if (IS_ENABLED(CONFIG_USB_DWC2_HOST))
  71. mode = USB_DR_MODE_HOST;
  72. else if (IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL))
  73. mode = USB_DR_MODE_PERIPHERAL;
  74. }
  75. if (mode != hsotg->dr_mode) {
  76. dev_warn(hsotg->dev,
  77. "Configuration mismatch. dr_mode forced to %s\n",
  78. mode == USB_DR_MODE_HOST ? "host" : "device");
  79. hsotg->dr_mode = mode;
  80. }
  81. return 0;
  82. }
  83. static int __dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg)
  84. {
  85. struct platform_device *pdev = to_platform_device(hsotg->dev);
  86. int ret;
  87. ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
  88. hsotg->supplies);
  89. if (ret)
  90. return ret;
  91. if (hsotg->utmi_clk) {
  92. ret = clk_prepare_enable(hsotg->utmi_clk);
  93. if (ret)
  94. goto err_dis_reg;
  95. }
  96. if (hsotg->clk) {
  97. ret = clk_prepare_enable(hsotg->clk);
  98. if (ret)
  99. goto err_dis_utmi_clk;
  100. }
  101. if (hsotg->uphy) {
  102. ret = usb_phy_init(hsotg->uphy);
  103. } else if (hsotg->plat && hsotg->plat->phy_init) {
  104. ret = hsotg->plat->phy_init(pdev, hsotg->plat->phy_type);
  105. } else {
  106. ret = phy_init(hsotg->phy);
  107. if (ret == 0) {
  108. ret = phy_power_on(hsotg->phy);
  109. if (ret)
  110. phy_exit(hsotg->phy);
  111. }
  112. }
  113. if (ret)
  114. goto err_dis_clk;
  115. return 0;
  116. err_dis_clk:
  117. if (hsotg->clk)
  118. clk_disable_unprepare(hsotg->clk);
  119. err_dis_utmi_clk:
  120. if (hsotg->utmi_clk)
  121. clk_disable_unprepare(hsotg->utmi_clk);
  122. err_dis_reg:
  123. regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), hsotg->supplies);
  124. return ret;
  125. }
  126. /**
  127. * dwc2_lowlevel_hw_enable - enable platform lowlevel hw resources
  128. * @hsotg: The driver state
  129. *
  130. * A wrapper for platform code responsible for controlling
  131. * low-level USB platform resources (phy, clock, regulators)
  132. */
  133. int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg)
  134. {
  135. int ret = __dwc2_lowlevel_hw_enable(hsotg);
  136. if (ret == 0)
  137. hsotg->ll_hw_enabled = true;
  138. return ret;
  139. }
  140. static int __dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg)
  141. {
  142. struct platform_device *pdev = to_platform_device(hsotg->dev);
  143. int ret = 0;
  144. if (hsotg->uphy) {
  145. usb_phy_shutdown(hsotg->uphy);
  146. } else if (hsotg->plat && hsotg->plat->phy_exit) {
  147. ret = hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type);
  148. } else {
  149. ret = phy_power_off(hsotg->phy);
  150. if (ret == 0)
  151. ret = phy_exit(hsotg->phy);
  152. }
  153. if (ret)
  154. return ret;
  155. if (hsotg->clk)
  156. clk_disable_unprepare(hsotg->clk);
  157. if (hsotg->utmi_clk)
  158. clk_disable_unprepare(hsotg->utmi_clk);
  159. return regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), hsotg->supplies);
  160. }
  161. /**
  162. * dwc2_lowlevel_hw_disable - disable platform lowlevel hw resources
  163. * @hsotg: The driver state
  164. *
  165. * A wrapper for platform code responsible for controlling
  166. * low-level USB platform resources (phy, clock, regulators)
  167. */
  168. int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg)
  169. {
  170. int ret = __dwc2_lowlevel_hw_disable(hsotg);
  171. if (ret == 0)
  172. hsotg->ll_hw_enabled = false;
  173. return ret;
  174. }
  175. static void dwc2_reset_control_assert(void *data)
  176. {
  177. reset_control_assert(data);
  178. }
  179. static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg)
  180. {
  181. int i, ret;
  182. hsotg->reset = devm_reset_control_get_optional(hsotg->dev, "dwc2");
  183. if (IS_ERR(hsotg->reset))
  184. return dev_err_probe(hsotg->dev, PTR_ERR(hsotg->reset),
  185. "error getting reset control\n");
  186. reset_control_deassert(hsotg->reset);
  187. ret = devm_add_action_or_reset(hsotg->dev, dwc2_reset_control_assert,
  188. hsotg->reset);
  189. if (ret)
  190. return ret;
  191. hsotg->reset_ecc = devm_reset_control_get_optional(hsotg->dev, "dwc2-ecc");
  192. if (IS_ERR(hsotg->reset_ecc))
  193. return dev_err_probe(hsotg->dev, PTR_ERR(hsotg->reset_ecc),
  194. "error getting reset control for ecc\n");
  195. reset_control_deassert(hsotg->reset_ecc);
  196. ret = devm_add_action_or_reset(hsotg->dev, dwc2_reset_control_assert,
  197. hsotg->reset_ecc);
  198. if (ret)
  199. return ret;
  200. /*
  201. * Attempt to find a generic PHY, then look for an old style
  202. * USB PHY and then fall back to pdata
  203. */
  204. hsotg->phy = devm_phy_get(hsotg->dev, "usb2-phy");
  205. if (IS_ERR(hsotg->phy)) {
  206. ret = PTR_ERR(hsotg->phy);
  207. switch (ret) {
  208. case -ENODEV:
  209. case -ENOSYS:
  210. hsotg->phy = NULL;
  211. break;
  212. default:
  213. return dev_err_probe(hsotg->dev, ret, "error getting phy\n");
  214. }
  215. }
  216. if (!hsotg->phy) {
  217. hsotg->uphy = devm_usb_get_phy(hsotg->dev, USB_PHY_TYPE_USB2);
  218. if (IS_ERR(hsotg->uphy)) {
  219. ret = PTR_ERR(hsotg->uphy);
  220. switch (ret) {
  221. case -ENODEV:
  222. case -ENXIO:
  223. hsotg->uphy = NULL;
  224. break;
  225. default:
  226. return dev_err_probe(hsotg->dev, ret, "error getting usb phy\n");
  227. }
  228. }
  229. }
  230. hsotg->plat = dev_get_platdata(hsotg->dev);
  231. /* Clock */
  232. hsotg->clk = devm_clk_get_optional(hsotg->dev, "otg");
  233. if (IS_ERR(hsotg->clk))
  234. return dev_err_probe(hsotg->dev, PTR_ERR(hsotg->clk), "cannot get otg clock\n");
  235. hsotg->utmi_clk = devm_clk_get_optional(hsotg->dev, "utmi");
  236. if (IS_ERR(hsotg->utmi_clk))
  237. return dev_err_probe(hsotg->dev, PTR_ERR(hsotg->utmi_clk),
  238. "cannot get utmi clock\n");
  239. /* Regulators */
  240. for (i = 0; i < ARRAY_SIZE(hsotg->supplies); i++)
  241. hsotg->supplies[i].supply = dwc2_hsotg_supply_names[i];
  242. ret = devm_regulator_bulk_get(hsotg->dev, ARRAY_SIZE(hsotg->supplies),
  243. hsotg->supplies);
  244. if (ret)
  245. return dev_err_probe(hsotg->dev, ret, "failed to request supplies\n");
  246. return 0;
  247. }
  248. /**
  249. * dwc2_driver_remove() - Called when the DWC_otg core is unregistered with the
  250. * DWC_otg driver
  251. *
  252. * @dev: Platform device
  253. *
  254. * This routine is called, for example, when the rmmod command is executed. The
  255. * device may or may not be electrically present. If it is present, the driver
  256. * stops device processing. Any resources used on behalf of this device are
  257. * freed.
  258. */
  259. static void dwc2_driver_remove(struct platform_device *dev)
  260. {
  261. struct dwc2_hsotg *hsotg = platform_get_drvdata(dev);
  262. struct dwc2_gregs_backup *gr;
  263. int ret = 0;
  264. gr = &hsotg->gr_backup;
  265. /* Exit Hibernation when driver is removed. */
  266. if (hsotg->hibernated) {
  267. if (gr->gotgctl & GOTGCTL_CURMODE_HOST)
  268. ret = dwc2_exit_hibernation(hsotg, 0, 0, 1);
  269. else
  270. ret = dwc2_exit_hibernation(hsotg, 0, 0, 0);
  271. if (ret)
  272. dev_err(hsotg->dev,
  273. "exit hibernation failed.\n");
  274. }
  275. /* Exit Partial Power Down when driver is removed. */
  276. if (hsotg->in_ppd) {
  277. ret = dwc2_exit_partial_power_down(hsotg, 0, true);
  278. if (ret)
  279. dev_err(hsotg->dev,
  280. "exit partial_power_down failed\n");
  281. }
  282. /* Exit clock gating when driver is removed. */
  283. if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_NONE &&
  284. hsotg->bus_suspended && !hsotg->params.no_clock_gating) {
  285. if (dwc2_is_device_mode(hsotg))
  286. dwc2_gadget_exit_clock_gating(hsotg, 0);
  287. else
  288. dwc2_host_exit_clock_gating(hsotg, 0);
  289. }
  290. dwc2_debugfs_exit(hsotg);
  291. if (hsotg->hcd_enabled)
  292. dwc2_hcd_remove(hsotg);
  293. if (hsotg->gadget_enabled)
  294. dwc2_hsotg_remove(hsotg);
  295. dwc2_drd_exit(hsotg);
  296. if (hsotg->params.activate_stm_id_vb_detection)
  297. regulator_disable(hsotg->usb33d);
  298. if (hsotg->ll_hw_enabled)
  299. dwc2_lowlevel_hw_disable(hsotg);
  300. }
  301. /**
  302. * dwc2_driver_shutdown() - Called on device shutdown
  303. *
  304. * @dev: Platform device
  305. *
  306. * In specific conditions (involving usb hubs) dwc2 devices can create a
  307. * lot of interrupts, even to the point of overwhelming devices running
  308. * at low frequencies. Some devices need to do special clock handling
  309. * at shutdown-time which may bring the system clock below the threshold
  310. * of being able to handle the dwc2 interrupts. Disabling dwc2-irqs
  311. * prevents reboots/poweroffs from getting stuck in such cases.
  312. */
  313. static void dwc2_driver_shutdown(struct platform_device *dev)
  314. {
  315. struct dwc2_hsotg *hsotg = platform_get_drvdata(dev);
  316. dwc2_disable_global_interrupts(hsotg);
  317. synchronize_irq(hsotg->irq);
  318. }
  319. /**
  320. * dwc2_check_core_endianness() - Returns true if core and AHB have
  321. * opposite endianness.
  322. * @hsotg: Programming view of the DWC_otg controller.
  323. */
  324. static bool dwc2_check_core_endianness(struct dwc2_hsotg *hsotg)
  325. {
  326. u32 snpsid;
  327. snpsid = ioread32(hsotg->regs + GSNPSID);
  328. if ((snpsid & GSNPSID_ID_MASK) == DWC2_OTG_ID ||
  329. (snpsid & GSNPSID_ID_MASK) == DWC2_FS_IOT_ID ||
  330. (snpsid & GSNPSID_ID_MASK) == DWC2_HS_IOT_ID)
  331. return false;
  332. return true;
  333. }
  334. /**
  335. * dwc2_check_core_version() - Check core version
  336. *
  337. * @hsotg: Programming view of the DWC_otg controller
  338. *
  339. */
  340. int dwc2_check_core_version(struct dwc2_hsotg *hsotg)
  341. {
  342. struct dwc2_hw_params *hw = &hsotg->hw_params;
  343. /*
  344. * Attempt to ensure this device is really a DWC_otg Controller.
  345. * Read and verify the GSNPSID register contents. The value should be
  346. * 0x45f4xxxx, 0x5531xxxx or 0x5532xxxx
  347. */
  348. hw->snpsid = dwc2_readl(hsotg, GSNPSID);
  349. if ((hw->snpsid & GSNPSID_ID_MASK) != DWC2_OTG_ID &&
  350. (hw->snpsid & GSNPSID_ID_MASK) != DWC2_FS_IOT_ID &&
  351. (hw->snpsid & GSNPSID_ID_MASK) != DWC2_HS_IOT_ID) {
  352. dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n",
  353. hw->snpsid);
  354. return -ENODEV;
  355. }
  356. dev_dbg(hsotg->dev, "Core Release: %1x.%1x%1x%1x (snpsid=%x)\n",
  357. hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf,
  358. hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid);
  359. return 0;
  360. }
  361. /**
  362. * dwc2_driver_probe() - Called when the DWC_otg core is bound to the DWC_otg
  363. * driver
  364. *
  365. * @dev: Platform device
  366. *
  367. * This routine creates the driver components required to control the device
  368. * (core, HCD, and PCD) and initializes the device. The driver components are
  369. * stored in a dwc2_hsotg structure. A reference to the dwc2_hsotg is saved
  370. * in the device private data. This allows the driver to access the dwc2_hsotg
  371. * structure on subsequent calls to driver methods for this device.
  372. */
  373. static int dwc2_driver_probe(struct platform_device *dev)
  374. {
  375. struct device_node *dn = dev->dev.of_node;
  376. struct dwc2_hsotg *hsotg;
  377. struct resource *res;
  378. int gpio_num;
  379. int retval;
  380. hsotg = devm_kzalloc(&dev->dev, sizeof(*hsotg), GFP_KERNEL);
  381. if (!hsotg)
  382. return -ENOMEM;
  383. hsotg->dev = &dev->dev;
  384. /*
  385. * Use reasonable defaults so platforms don't have to provide these.
  386. */
  387. if (!dev->dev.dma_mask)
  388. dev->dev.dma_mask = &dev->dev.coherent_dma_mask;
  389. retval = dma_set_coherent_mask(&dev->dev, DMA_BIT_MASK(32));
  390. if (retval) {
  391. dev_err(&dev->dev, "can't set coherent DMA mask: %d\n", retval);
  392. return retval;
  393. }
  394. hsotg->regs = devm_platform_get_and_ioremap_resource(dev, 0, &res);
  395. if (IS_ERR(hsotg->regs))
  396. return PTR_ERR(hsotg->regs);
  397. dev_dbg(&dev->dev, "mapped PA %08lx to VA %p\n",
  398. (unsigned long)res->start, hsotg->regs);
  399. /*hsotg->sys_regs = devm_platform_get_and_ioremap_resource(dev, 1, &res);
  400. if (IS_ERR(hsotg->sys_regs)) {printk("%s:%d\n", __func__, __LINE__);
  401. return PTR_ERR(hsotg->regs);
  402. }*/
  403. res = platform_get_resource(dev, IORESOURCE_MEM, 1);
  404. if (!res) {
  405. dev_err(&dev->dev, "Failed to get sys_base memory.\n");
  406. return -EINVAL;
  407. }
  408. hsotg->sys_regs = ioremap(res->start, resource_size(res));
  409. if(IS_ERR(hsotg->sys_regs)) {
  410. dev_err(&dev->dev, "Failed to devm_ioremap_resource\n");
  411. return PTR_ERR(hsotg->sys_regs);
  412. }
  413. retval = of_property_read_u32(dn, "usb-id-reg", &hsotg->usb_id_reg);
  414. if(retval == 0) {
  415. retval = of_property_read_u32(dn, "usb-id-bit-offset", &hsotg->usb_id_bit_offset);
  416. if(retval) {
  417. hsotg->usb_id_bit_offset = -1;
  418. }
  419. } else {
  420. hsotg->usb_id_reg = -1;
  421. hsotg->usb_id_bit_offset = -1;
  422. }
  423. gpio_num = of_get_named_gpio(dev->dev.of_node, "reset-gpio", 0);
  424. if (gpio_num < 0) {
  425. printk("Not use usb reset gpio.\n");
  426. hsotg->gpiod_reset = NULL;
  427. } else {
  428. hsotg->gpiod_reset = gpio_to_desc(gpio_num);
  429. if (IS_ERR(hsotg->gpiod_reset)) {
  430. dev_err(&dev->dev, "Failed to get usb reset gpio.\n");
  431. }
  432. }
  433. retval = dwc2_lowlevel_hw_init(hsotg);
  434. if (retval)
  435. return retval;
  436. spin_lock_init(&hsotg->lock);
  437. hsotg->vbus_supply = devm_regulator_get_optional(hsotg->dev, "vbus");
  438. if (IS_ERR(hsotg->vbus_supply)) {
  439. retval = PTR_ERR(hsotg->vbus_supply);
  440. hsotg->vbus_supply = NULL;
  441. if (retval != -ENODEV)
  442. return retval;
  443. }
  444. retval = dwc2_lowlevel_hw_enable(hsotg);
  445. if (retval)
  446. return retval;
  447. hsotg->needs_byte_swap = dwc2_check_core_endianness(hsotg);
  448. retval = dwc2_get_dr_mode(hsotg);
  449. if (retval)
  450. goto error;
  451. hsotg->need_phy_for_wake =
  452. of_property_read_bool(dev->dev.of_node,
  453. "snps,need-phy-for-wake");
  454. /*
  455. * Before performing any core related operations
  456. * check core version.
  457. */
  458. retval = dwc2_check_core_version(hsotg);
  459. if (retval)
  460. goto error;
  461. /*
  462. * Reset before dwc2_get_hwparams() then it could get power-on real
  463. * reset value form registers.
  464. */
  465. retval = dwc2_core_reset(hsotg, false);
  466. if (retval)
  467. goto error;
  468. /* Detect config values from hardware */
  469. retval = dwc2_get_hwparams(hsotg);
  470. if (retval)
  471. goto error;
  472. hsotg->irq = platform_get_irq(dev, 0);
  473. if (hsotg->irq < 0) {
  474. retval = hsotg->irq;
  475. goto error;
  476. }
  477. dev_dbg(hsotg->dev, "registering common handler for irq%d\n",
  478. hsotg->irq);
  479. retval = devm_request_irq(hsotg->dev, hsotg->irq,
  480. dwc2_handle_common_intr, IRQF_SHARED,
  481. dev_name(hsotg->dev), hsotg);
  482. if (retval)
  483. goto error;
  484. /*
  485. * For OTG cores, set the force mode bits to reflect the value
  486. * of dr_mode. Force mode bits should not be touched at any
  487. * other time after this.
  488. */
  489. dwc2_force_dr_mode(hsotg);
  490. retval = dwc2_init_params(hsotg);
  491. if (retval)
  492. goto error;
  493. if (hsotg->params.activate_stm_id_vb_detection) {
  494. u32 ggpio;
  495. hsotg->usb33d = devm_regulator_get(hsotg->dev, "usb33d");
  496. if (IS_ERR(hsotg->usb33d)) {
  497. retval = PTR_ERR(hsotg->usb33d);
  498. dev_err_probe(hsotg->dev, retval, "failed to request usb33d supply\n");
  499. goto error;
  500. }
  501. retval = regulator_enable(hsotg->usb33d);
  502. if (retval) {
  503. dev_err_probe(hsotg->dev, retval, "failed to enable usb33d supply\n");
  504. goto error;
  505. }
  506. ggpio = dwc2_readl(hsotg, GGPIO);
  507. ggpio |= GGPIO_STM32_OTG_GCCFG_IDEN;
  508. ggpio |= GGPIO_STM32_OTG_GCCFG_VBDEN;
  509. dwc2_writel(hsotg, ggpio, GGPIO);
  510. /* ID/VBUS detection startup time */
  511. usleep_range(5000, 7000);
  512. }
  513. retval = dwc2_drd_init(hsotg);
  514. if (retval) {
  515. dev_err_probe(hsotg->dev, retval, "failed to initialize dual-role\n");
  516. goto error_init;
  517. }
  518. if (hsotg->dr_mode != USB_DR_MODE_HOST) {
  519. retval = dwc2_gadget_init(hsotg);
  520. if (retval)
  521. goto error_drd;
  522. hsotg->gadget_enabled = 1;
  523. }
  524. /*
  525. * If we need PHY for wakeup we must be wakeup capable.
  526. * When we have a device that can wake without the PHY we
  527. * can adjust this condition.
  528. */
  529. if (hsotg->need_phy_for_wake)
  530. device_set_wakeup_capable(&dev->dev, true);
  531. hsotg->reset_phy_on_wake =
  532. of_property_read_bool(dev->dev.of_node,
  533. "snps,reset-phy-on-wake");
  534. if (hsotg->reset_phy_on_wake && !hsotg->phy) {
  535. dev_warn(hsotg->dev,
  536. "Quirk reset-phy-on-wake only supports generic PHYs\n");
  537. hsotg->reset_phy_on_wake = false;
  538. }
  539. if (hsotg->dr_mode != USB_DR_MODE_PERIPHERAL) {
  540. retval = dwc2_hcd_init(hsotg);
  541. if (retval) {
  542. if (hsotg->gadget_enabled)
  543. dwc2_hsotg_remove(hsotg);
  544. goto error_drd;
  545. }
  546. hsotg->hcd_enabled = 1;
  547. }
  548. platform_set_drvdata(dev, hsotg);
  549. hsotg->hibernated = 0;
  550. dwc2_debugfs_init(hsotg);
  551. /* Gadget code manages lowlevel hw on its own */
  552. if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
  553. dwc2_lowlevel_hw_disable(hsotg);
  554. #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
  555. IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
  556. /* Postponed adding a new gadget to the udc class driver list */
  557. if (hsotg->gadget_enabled) {
  558. retval = usb_add_gadget_udc(hsotg->dev, &hsotg->gadget);
  559. if (retval) {
  560. hsotg->gadget.udc = NULL;
  561. dwc2_hsotg_remove(hsotg);
  562. goto error_debugfs;
  563. }
  564. }
  565. #endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */
  566. return 0;
  567. #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
  568. IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
  569. error_debugfs:
  570. dwc2_debugfs_exit(hsotg);
  571. if (hsotg->hcd_enabled)
  572. dwc2_hcd_remove(hsotg);
  573. #endif
  574. error_drd:
  575. dwc2_drd_exit(hsotg);
  576. error_init:
  577. if (hsotg->params.activate_stm_id_vb_detection)
  578. regulator_disable(hsotg->usb33d);
  579. error:
  580. if (hsotg->ll_hw_enabled)
  581. dwc2_lowlevel_hw_disable(hsotg);
  582. return retval;
  583. }
  584. static int __maybe_unused dwc2_suspend(struct device *dev)
  585. {
  586. struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
  587. bool is_device_mode = dwc2_is_device_mode(dwc2);
  588. int ret = 0;
  589. if (is_device_mode)
  590. dwc2_hsotg_suspend(dwc2);
  591. dwc2_drd_suspend(dwc2);
  592. if (dwc2->params.activate_stm_id_vb_detection) {
  593. unsigned long flags;
  594. u32 ggpio, gotgctl;
  595. /*
  596. * Need to force the mode to the current mode to avoid Mode
  597. * Mismatch Interrupt when ID detection will be disabled.
  598. */
  599. dwc2_force_mode(dwc2, !is_device_mode);
  600. spin_lock_irqsave(&dwc2->lock, flags);
  601. gotgctl = dwc2_readl(dwc2, GOTGCTL);
  602. /* bypass debounce filter, enable overrides */
  603. gotgctl |= GOTGCTL_DBNCE_FLTR_BYPASS;
  604. gotgctl |= GOTGCTL_BVALOEN | GOTGCTL_AVALOEN;
  605. /* Force A / B session if needed */
  606. if (gotgctl & GOTGCTL_ASESVLD)
  607. gotgctl |= GOTGCTL_AVALOVAL;
  608. if (gotgctl & GOTGCTL_BSESVLD)
  609. gotgctl |= GOTGCTL_BVALOVAL;
  610. dwc2_writel(dwc2, gotgctl, GOTGCTL);
  611. spin_unlock_irqrestore(&dwc2->lock, flags);
  612. ggpio = dwc2_readl(dwc2, GGPIO);
  613. ggpio &= ~GGPIO_STM32_OTG_GCCFG_IDEN;
  614. ggpio &= ~GGPIO_STM32_OTG_GCCFG_VBDEN;
  615. dwc2_writel(dwc2, ggpio, GGPIO);
  616. regulator_disable(dwc2->usb33d);
  617. }
  618. if (dwc2->ll_hw_enabled &&
  619. (is_device_mode || dwc2_host_can_poweroff_phy(dwc2))) {
  620. ret = __dwc2_lowlevel_hw_disable(dwc2);
  621. dwc2->phy_off_for_suspend = true;
  622. }
  623. return ret;
  624. }
  625. static int __maybe_unused dwc2_resume(struct device *dev)
  626. {
  627. struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
  628. int ret = 0;
  629. if (dwc2->phy_off_for_suspend && dwc2->ll_hw_enabled) {
  630. ret = __dwc2_lowlevel_hw_enable(dwc2);
  631. if (ret)
  632. return ret;
  633. }
  634. dwc2->phy_off_for_suspend = false;
  635. if (dwc2->params.activate_stm_id_vb_detection) {
  636. unsigned long flags;
  637. u32 ggpio, gotgctl;
  638. ret = regulator_enable(dwc2->usb33d);
  639. if (ret)
  640. return ret;
  641. ggpio = dwc2_readl(dwc2, GGPIO);
  642. ggpio |= GGPIO_STM32_OTG_GCCFG_IDEN;
  643. ggpio |= GGPIO_STM32_OTG_GCCFG_VBDEN;
  644. dwc2_writel(dwc2, ggpio, GGPIO);
  645. /* ID/VBUS detection startup time */
  646. usleep_range(5000, 7000);
  647. spin_lock_irqsave(&dwc2->lock, flags);
  648. gotgctl = dwc2_readl(dwc2, GOTGCTL);
  649. gotgctl &= ~GOTGCTL_DBNCE_FLTR_BYPASS;
  650. gotgctl &= ~(GOTGCTL_BVALOEN | GOTGCTL_AVALOEN |
  651. GOTGCTL_BVALOVAL | GOTGCTL_AVALOVAL);
  652. dwc2_writel(dwc2, gotgctl, GOTGCTL);
  653. spin_unlock_irqrestore(&dwc2->lock, flags);
  654. }
  655. if (!dwc2->role_sw) {
  656. /* Need to restore FORCEDEVMODE/FORCEHOSTMODE */
  657. dwc2_force_dr_mode(dwc2);
  658. } else {
  659. dwc2_drd_resume(dwc2);
  660. }
  661. if (dwc2_is_device_mode(dwc2))
  662. ret = dwc2_hsotg_resume(dwc2);
  663. return ret;
  664. }
  665. static const struct dev_pm_ops dwc2_dev_pm_ops = {
  666. SET_SYSTEM_SLEEP_PM_OPS(dwc2_suspend, dwc2_resume)
  667. };
  668. static struct platform_driver dwc2_platform_driver = {
  669. .driver = {
  670. .name = dwc2_driver_name,
  671. .of_match_table = dwc2_of_match_table,
  672. .acpi_match_table = ACPI_PTR(dwc2_acpi_match),
  673. .pm = &dwc2_dev_pm_ops,
  674. },
  675. .probe = dwc2_driver_probe,
  676. .remove_new = dwc2_driver_remove,
  677. .shutdown = dwc2_driver_shutdown,
  678. };
  679. module_platform_driver(dwc2_platform_driver);