gus_dma.c 6.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Routines for GF1 DMA control
  4. * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
  5. */
  6. #include <asm/dma.h>
  7. #include <linux/slab.h>
  8. #include <sound/core.h>
  9. #include <sound/gus.h>
  10. static void snd_gf1_dma_ack(struct snd_gus_card * gus)
  11. {
  12. unsigned long flags;
  13. spin_lock_irqsave(&gus->reg_lock, flags);
  14. snd_gf1_write8(gus, SNDRV_GF1_GB_DRAM_DMA_CONTROL, 0x00);
  15. snd_gf1_look8(gus, SNDRV_GF1_GB_DRAM_DMA_CONTROL);
  16. spin_unlock_irqrestore(&gus->reg_lock, flags);
  17. }
  18. static void snd_gf1_dma_program(struct snd_gus_card * gus,
  19. unsigned int addr,
  20. unsigned long buf_addr,
  21. unsigned int count,
  22. unsigned int cmd)
  23. {
  24. unsigned long flags;
  25. unsigned int address;
  26. unsigned char dma_cmd;
  27. unsigned int address_high;
  28. dev_dbg(gus->card->dev,
  29. "dma_transfer: addr=0x%x, buf=0x%lx, count=0x%x\n",
  30. addr, buf_addr, count);
  31. if (gus->gf1.dma1 > 3) {
  32. if (gus->gf1.enh_mode) {
  33. address = addr >> 1;
  34. } else {
  35. if (addr & 0x1f) {
  36. dev_dbg(gus->card->dev,
  37. "%s: unaligned address (0x%x)?\n",
  38. __func__, addr);
  39. return;
  40. }
  41. address = (addr & 0x000c0000) | ((addr & 0x0003ffff) >> 1);
  42. }
  43. } else {
  44. address = addr;
  45. }
  46. dma_cmd = SNDRV_GF1_DMA_ENABLE | (unsigned short) cmd;
  47. #if 0
  48. dma_cmd |= 0x08;
  49. #endif
  50. if (dma_cmd & SNDRV_GF1_DMA_16BIT) {
  51. count++;
  52. count &= ~1; /* align */
  53. }
  54. if (gus->gf1.dma1 > 3) {
  55. dma_cmd |= SNDRV_GF1_DMA_WIDTH16;
  56. count++;
  57. count &= ~1; /* align */
  58. }
  59. snd_gf1_dma_ack(gus);
  60. snd_dma_program(gus->gf1.dma1, buf_addr, count, dma_cmd & SNDRV_GF1_DMA_READ ? DMA_MODE_READ : DMA_MODE_WRITE);
  61. #if 0
  62. dev_dbg(gus->card->dev,
  63. "address = 0x%x, count = 0x%x, dma_cmd = 0x%x\n",
  64. address << 1, count, dma_cmd);
  65. #endif
  66. spin_lock_irqsave(&gus->reg_lock, flags);
  67. if (gus->gf1.enh_mode) {
  68. address_high = ((address >> 16) & 0x000000f0) | (address & 0x0000000f);
  69. snd_gf1_write16(gus, SNDRV_GF1_GW_DRAM_DMA_LOW, (unsigned short) (address >> 4));
  70. snd_gf1_write8(gus, SNDRV_GF1_GB_DRAM_DMA_HIGH, (unsigned char) address_high);
  71. } else
  72. snd_gf1_write16(gus, SNDRV_GF1_GW_DRAM_DMA_LOW, (unsigned short) (address >> 4));
  73. snd_gf1_write8(gus, SNDRV_GF1_GB_DRAM_DMA_CONTROL, dma_cmd);
  74. spin_unlock_irqrestore(&gus->reg_lock, flags);
  75. }
  76. static struct snd_gf1_dma_block *snd_gf1_dma_next_block(struct snd_gus_card * gus)
  77. {
  78. struct snd_gf1_dma_block *block;
  79. /* PCM block have bigger priority than synthesizer one */
  80. if (gus->gf1.dma_data_pcm) {
  81. block = gus->gf1.dma_data_pcm;
  82. if (gus->gf1.dma_data_pcm_last == block) {
  83. gus->gf1.dma_data_pcm =
  84. gus->gf1.dma_data_pcm_last = NULL;
  85. } else {
  86. gus->gf1.dma_data_pcm = block->next;
  87. }
  88. } else if (gus->gf1.dma_data_synth) {
  89. block = gus->gf1.dma_data_synth;
  90. if (gus->gf1.dma_data_synth_last == block) {
  91. gus->gf1.dma_data_synth =
  92. gus->gf1.dma_data_synth_last = NULL;
  93. } else {
  94. gus->gf1.dma_data_synth = block->next;
  95. }
  96. } else {
  97. block = NULL;
  98. }
  99. if (block) {
  100. gus->gf1.dma_ack = block->ack;
  101. gus->gf1.dma_private_data = block->private_data;
  102. }
  103. return block;
  104. }
  105. static void snd_gf1_dma_interrupt(struct snd_gus_card * gus)
  106. {
  107. struct snd_gf1_dma_block *block;
  108. snd_gf1_dma_ack(gus);
  109. if (gus->gf1.dma_ack)
  110. gus->gf1.dma_ack(gus, gus->gf1.dma_private_data);
  111. spin_lock(&gus->dma_lock);
  112. if (gus->gf1.dma_data_pcm == NULL &&
  113. gus->gf1.dma_data_synth == NULL) {
  114. gus->gf1.dma_ack = NULL;
  115. gus->gf1.dma_flags &= ~SNDRV_GF1_DMA_TRIGGER;
  116. spin_unlock(&gus->dma_lock);
  117. return;
  118. }
  119. block = snd_gf1_dma_next_block(gus);
  120. spin_unlock(&gus->dma_lock);
  121. if (!block)
  122. return;
  123. snd_gf1_dma_program(gus, block->addr, block->buf_addr, block->count, (unsigned short) block->cmd);
  124. kfree(block);
  125. #if 0
  126. dev_dbg(gus->card->dev,
  127. "program dma (IRQ) - addr = 0x%x, buffer = 0x%lx, count = 0x%x, cmd = 0x%x\n",
  128. block->addr, block->buf_addr, block->count, block->cmd);
  129. #endif
  130. }
  131. int snd_gf1_dma_init(struct snd_gus_card * gus)
  132. {
  133. mutex_lock(&gus->dma_mutex);
  134. gus->gf1.dma_shared++;
  135. if (gus->gf1.dma_shared > 1) {
  136. mutex_unlock(&gus->dma_mutex);
  137. return 0;
  138. }
  139. gus->gf1.interrupt_handler_dma_write = snd_gf1_dma_interrupt;
  140. gus->gf1.dma_data_pcm =
  141. gus->gf1.dma_data_pcm_last =
  142. gus->gf1.dma_data_synth =
  143. gus->gf1.dma_data_synth_last = NULL;
  144. mutex_unlock(&gus->dma_mutex);
  145. return 0;
  146. }
  147. int snd_gf1_dma_done(struct snd_gus_card * gus)
  148. {
  149. struct snd_gf1_dma_block *block;
  150. mutex_lock(&gus->dma_mutex);
  151. gus->gf1.dma_shared--;
  152. if (!gus->gf1.dma_shared) {
  153. snd_dma_disable(gus->gf1.dma1);
  154. snd_gf1_set_default_handlers(gus, SNDRV_GF1_HANDLER_DMA_WRITE);
  155. snd_gf1_dma_ack(gus);
  156. while ((block = gus->gf1.dma_data_pcm)) {
  157. gus->gf1.dma_data_pcm = block->next;
  158. kfree(block);
  159. }
  160. while ((block = gus->gf1.dma_data_synth)) {
  161. gus->gf1.dma_data_synth = block->next;
  162. kfree(block);
  163. }
  164. gus->gf1.dma_data_pcm_last =
  165. gus->gf1.dma_data_synth_last = NULL;
  166. }
  167. mutex_unlock(&gus->dma_mutex);
  168. return 0;
  169. }
  170. int snd_gf1_dma_transfer_block(struct snd_gus_card * gus,
  171. struct snd_gf1_dma_block * __block,
  172. int atomic,
  173. int synth)
  174. {
  175. unsigned long flags;
  176. struct snd_gf1_dma_block *block;
  177. block = kmalloc(sizeof(*block), atomic ? GFP_ATOMIC : GFP_KERNEL);
  178. if (!block)
  179. return -ENOMEM;
  180. *block = *__block;
  181. block->next = NULL;
  182. dev_dbg(gus->card->dev,
  183. "addr = 0x%x, buffer = 0x%lx, count = 0x%x, cmd = 0x%x\n",
  184. block->addr, (long) block->buffer, block->count,
  185. block->cmd);
  186. dev_dbg(gus->card->dev,
  187. "gus->gf1.dma_data_pcm_last = 0x%lx\n",
  188. (long)gus->gf1.dma_data_pcm_last);
  189. dev_dbg(gus->card->dev,
  190. "gus->gf1.dma_data_pcm = 0x%lx\n",
  191. (long)gus->gf1.dma_data_pcm);
  192. spin_lock_irqsave(&gus->dma_lock, flags);
  193. if (synth) {
  194. if (gus->gf1.dma_data_synth_last) {
  195. gus->gf1.dma_data_synth_last->next = block;
  196. gus->gf1.dma_data_synth_last = block;
  197. } else {
  198. gus->gf1.dma_data_synth =
  199. gus->gf1.dma_data_synth_last = block;
  200. }
  201. } else {
  202. if (gus->gf1.dma_data_pcm_last) {
  203. gus->gf1.dma_data_pcm_last->next = block;
  204. gus->gf1.dma_data_pcm_last = block;
  205. } else {
  206. gus->gf1.dma_data_pcm =
  207. gus->gf1.dma_data_pcm_last = block;
  208. }
  209. }
  210. if (!(gus->gf1.dma_flags & SNDRV_GF1_DMA_TRIGGER)) {
  211. gus->gf1.dma_flags |= SNDRV_GF1_DMA_TRIGGER;
  212. block = snd_gf1_dma_next_block(gus);
  213. spin_unlock_irqrestore(&gus->dma_lock, flags);
  214. if (block == NULL)
  215. return 0;
  216. snd_gf1_dma_program(gus, block->addr, block->buf_addr, block->count, (unsigned short) block->cmd);
  217. kfree(block);
  218. return 0;
  219. }
  220. spin_unlock_irqrestore(&gus->dma_lock, flags);
  221. return 0;
  222. }