ast_i2c.c 8.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012-2020 ASPEED Technology Inc.
  4. * Copyright 2016 IBM Corporation
  5. * Copyright 2017 Google, Inc.
  6. */
  7. #include <common.h>
  8. #include <clk.h>
  9. #include <dm.h>
  10. #include <errno.h>
  11. #include <fdtdec.h>
  12. #include <i2c.h>
  13. #include <log.h>
  14. #include <asm/io.h>
  15. #include <asm/arch/scu_ast2500.h>
  16. #include <linux/delay.h>
  17. #include <linux/err.h>
  18. #include <reset.h>
  19. #include "ast_i2c.h"
  20. #define I2C_TIMEOUT_US 100000
  21. #define I2C_SLEEP_STEP_US 20
  22. #define HIGHSPEED_TTIMEOUT 3
  23. /*
  24. * Device private data
  25. */
  26. struct ast_i2c_priv {
  27. /* This device's clock */
  28. struct clk clk;
  29. /* Device registers */
  30. struct ast_i2c_regs *regs;
  31. /* I2C speed in Hz */
  32. int speed;
  33. };
  34. /*
  35. * Given desired divider ratio, return the value that needs to be set
  36. * in Clock and AC Timing Control register
  37. */
  38. static u32 get_clk_reg_val(ulong divider_ratio)
  39. {
  40. ulong inc = 0, div;
  41. ulong scl_low, scl_high, data;
  42. for (div = 0; divider_ratio >= 16; div++) {
  43. inc |= (divider_ratio & 1);
  44. divider_ratio >>= 1;
  45. }
  46. divider_ratio += inc;
  47. scl_low = (divider_ratio >> 1) - 1;
  48. scl_high = divider_ratio - scl_low - 2;
  49. data = I2CD_CACTC_BASE
  50. | (scl_high << I2CD_TCKHIGH_SHIFT)
  51. | (scl_low << I2CD_TCKLOW_SHIFT)
  52. | (div << I2CD_BASE_DIV_SHIFT);
  53. return data;
  54. }
  55. static void ast_i2c_clear_interrupts(struct udevice *dev)
  56. {
  57. struct ast_i2c_priv *priv = dev_get_priv(dev);
  58. writel(~0, &priv->regs->isr);
  59. }
  60. static void ast_i2c_init_bus(struct udevice *dev)
  61. {
  62. struct ast_i2c_priv *priv = dev_get_priv(dev);
  63. /* Reset device */
  64. writel(0, &priv->regs->fcr);
  65. /* Enable Master Mode. Assuming single-master */
  66. writel(I2CD_MASTER_EN
  67. | I2CD_M_SDA_LOCK_EN
  68. | I2CD_MULTI_MASTER_DIS,
  69. &priv->regs->fcr);
  70. /* Enable Interrupts */
  71. writel(I2CD_INTR_TX_ACK
  72. | I2CD_INTR_TX_NAK
  73. | I2CD_INTR_RX_DONE
  74. | I2CD_INTR_BUS_RECOVER_DONE
  75. | I2CD_INTR_NORMAL_STOP
  76. | I2CD_INTR_ABNORMAL, &priv->regs->icr);
  77. }
  78. static int ast_i2c_of_to_plat(struct udevice *dev)
  79. {
  80. struct ast_i2c_priv *priv = dev_get_priv(dev);
  81. int ret;
  82. priv->regs = dev_read_addr_ptr(dev);
  83. if (!priv->regs)
  84. return -EINVAL;
  85. ret = clk_get_by_index(dev, 0, &priv->clk);
  86. if (ret < 0) {
  87. debug("%s: Can't get clock for %s: %d\n", __func__, dev->name,
  88. ret);
  89. return ret;
  90. }
  91. return 0;
  92. }
  93. static int ast_i2c_probe(struct udevice *dev)
  94. {
  95. struct reset_ctl reset_ctl;
  96. int rc;
  97. debug("Enabling I2C%u\n", dev_seq(dev));
  98. /*
  99. * Get all I2C devices out of Reset.
  100. *
  101. * Only needs to be done once so test before performing reset.
  102. */
  103. rc = reset_get_by_index(dev, 0, &reset_ctl);
  104. if (rc) {
  105. printf("%s: Failed to get reset signal\n", __func__);
  106. return rc;
  107. }
  108. if (reset_status(&reset_ctl) > 0) {
  109. reset_assert(&reset_ctl);
  110. reset_deassert(&reset_ctl);
  111. }
  112. ast_i2c_init_bus(dev);
  113. return 0;
  114. }
  115. static int ast_i2c_wait_isr(struct udevice *dev, u32 flag)
  116. {
  117. struct ast_i2c_priv *priv = dev_get_priv(dev);
  118. int timeout = I2C_TIMEOUT_US;
  119. while (!(readl(&priv->regs->isr) & flag) && timeout > 0) {
  120. udelay(I2C_SLEEP_STEP_US);
  121. timeout -= I2C_SLEEP_STEP_US;
  122. }
  123. ast_i2c_clear_interrupts(dev);
  124. if (timeout <= 0)
  125. return -ETIMEDOUT;
  126. return 0;
  127. }
  128. static int ast_i2c_send_stop(struct udevice *dev)
  129. {
  130. struct ast_i2c_priv *priv = dev_get_priv(dev);
  131. writel(I2CD_M_STOP_CMD, &priv->regs->csr);
  132. return ast_i2c_wait_isr(dev, I2CD_INTR_NORMAL_STOP);
  133. }
  134. static int ast_i2c_wait_tx(struct udevice *dev)
  135. {
  136. struct ast_i2c_priv *priv = dev_get_priv(dev);
  137. int timeout = I2C_TIMEOUT_US;
  138. u32 flag = I2CD_INTR_TX_ACK | I2CD_INTR_TX_NAK;
  139. u32 status = readl(&priv->regs->isr) & flag;
  140. int ret = 0;
  141. while (!status && timeout > 0) {
  142. status = readl(&priv->regs->isr) & flag;
  143. udelay(I2C_SLEEP_STEP_US);
  144. timeout -= I2C_SLEEP_STEP_US;
  145. }
  146. if (status == I2CD_INTR_TX_NAK)
  147. ret = -EREMOTEIO;
  148. if (timeout <= 0)
  149. ret = -ETIMEDOUT;
  150. ast_i2c_clear_interrupts(dev);
  151. return ret;
  152. }
  153. static int ast_i2c_start_txn(struct udevice *dev, uint devaddr)
  154. {
  155. struct ast_i2c_priv *priv = dev_get_priv(dev);
  156. /* Start and Send Device Address */
  157. writel(devaddr, &priv->regs->trbbr);
  158. writel(I2CD_M_START_CMD | I2CD_M_TX_CMD, &priv->regs->csr);
  159. return ast_i2c_wait_tx(dev);
  160. }
  161. static int ast_i2c_read_data(struct udevice *dev, u8 chip_addr, u8 *buffer,
  162. size_t len, bool send_stop)
  163. {
  164. struct ast_i2c_priv *priv = dev_get_priv(dev);
  165. u32 i2c_cmd = I2CD_M_RX_CMD;
  166. int ret;
  167. ret = ast_i2c_start_txn(dev, (chip_addr << 1) | I2C_M_RD);
  168. if (ret < 0)
  169. return ret;
  170. for (; len > 0; len--, buffer++) {
  171. if (len == 1)
  172. i2c_cmd |= I2CD_M_S_RX_CMD_LAST;
  173. writel(i2c_cmd, &priv->regs->csr);
  174. ret = ast_i2c_wait_isr(dev, I2CD_INTR_RX_DONE);
  175. if (ret < 0)
  176. return ret;
  177. *buffer = (readl(&priv->regs->trbbr) & I2CD_RX_DATA_MASK)
  178. >> I2CD_RX_DATA_SHIFT;
  179. }
  180. ast_i2c_clear_interrupts(dev);
  181. if (send_stop)
  182. return ast_i2c_send_stop(dev);
  183. return 0;
  184. }
  185. static int ast_i2c_write_data(struct udevice *dev, u8 chip_addr, u8
  186. *buffer, size_t len, bool send_stop)
  187. {
  188. struct ast_i2c_priv *priv = dev_get_priv(dev);
  189. int ret;
  190. ret = ast_i2c_start_txn(dev, (chip_addr << 1));
  191. if (ret < 0)
  192. return ret;
  193. for (; len > 0; len--, buffer++) {
  194. writel(*buffer, &priv->regs->trbbr);
  195. writel(I2CD_M_TX_CMD, &priv->regs->csr);
  196. ret = ast_i2c_wait_tx(dev);
  197. if (ret < 0)
  198. return ret;
  199. }
  200. if (send_stop)
  201. return ast_i2c_send_stop(dev);
  202. return 0;
  203. }
  204. static int ast_i2c_deblock(struct udevice *dev)
  205. {
  206. struct ast_i2c_priv *priv = dev_get_priv(dev);
  207. struct ast_i2c_regs *regs = priv->regs;
  208. u32 csr = readl(&regs->csr);
  209. bool sda_high = csr & I2CD_SDA_LINE_STS;
  210. bool scl_high = csr & I2CD_SCL_LINE_STS;
  211. int ret = 0;
  212. if (sda_high && scl_high) {
  213. /* Bus is idle, no deblocking needed. */
  214. return 0;
  215. } else if (sda_high) {
  216. /* Send stop command */
  217. debug("Unterminated TXN in (%x), sending stop\n", csr);
  218. ret = ast_i2c_send_stop(dev);
  219. } else if (scl_high) {
  220. /* Possibly stuck slave */
  221. debug("Bus stuck (%x), attempting recovery\n", csr);
  222. writel(I2CD_BUS_RECOVER_CMD, &regs->csr);
  223. ret = ast_i2c_wait_isr(dev, I2CD_INTR_BUS_RECOVER_DONE);
  224. } else {
  225. /* Just try to reinit the device. */
  226. ast_i2c_init_bus(dev);
  227. }
  228. return ret;
  229. }
  230. static int ast_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs)
  231. {
  232. int ret;
  233. ret = ast_i2c_deblock(dev);
  234. if (ret < 0)
  235. return ret;
  236. debug("i2c_xfer: %d messages\n", nmsgs);
  237. for (; nmsgs > 0; nmsgs--, msg++) {
  238. if (msg->flags & I2C_M_RD) {
  239. debug("i2c_read: chip=0x%x, len=0x%x, flags=0x%x\n",
  240. msg->addr, msg->len, msg->flags);
  241. ret = ast_i2c_read_data(dev, msg->addr, msg->buf,
  242. msg->len, (nmsgs == 1));
  243. } else {
  244. debug("i2c_write: chip=0x%x, len=0x%x, flags=0x%x\n",
  245. msg->addr, msg->len, msg->flags);
  246. ret = ast_i2c_write_data(dev, msg->addr, msg->buf,
  247. msg->len, (nmsgs == 1));
  248. }
  249. if (ret) {
  250. debug("%s: error (%d)\n", __func__, ret);
  251. return -EREMOTEIO;
  252. }
  253. }
  254. return 0;
  255. }
  256. static int ast_i2c_set_speed(struct udevice *dev, unsigned int speed)
  257. {
  258. struct ast_i2c_priv *priv = dev_get_priv(dev);
  259. struct ast_i2c_regs *regs = priv->regs;
  260. ulong i2c_rate, divider;
  261. debug("Setting speed for I2C%d to <%u>\n", dev_seq(dev), speed);
  262. if (!speed) {
  263. debug("No valid speed specified\n");
  264. return -EINVAL;
  265. }
  266. i2c_rate = clk_get_rate(&priv->clk);
  267. divider = i2c_rate / speed;
  268. priv->speed = speed;
  269. if (speed > I2C_SPEED_FAST_RATE) {
  270. debug("Enable High Speed\n");
  271. setbits_le32(&regs->fcr, I2CD_M_HIGH_SPEED_EN
  272. | I2CD_M_SDA_DRIVE_1T_EN
  273. | I2CD_SDA_DRIVE_1T_EN);
  274. writel(HIGHSPEED_TTIMEOUT, &regs->cactcr2);
  275. } else {
  276. debug("Enabling Normal Speed\n");
  277. writel(I2CD_NO_TIMEOUT_CTRL, &regs->cactcr2);
  278. }
  279. writel(get_clk_reg_val(divider), &regs->cactcr1);
  280. ast_i2c_clear_interrupts(dev);
  281. return 0;
  282. }
  283. static const struct dm_i2c_ops ast_i2c_ops = {
  284. .xfer = ast_i2c_xfer,
  285. .set_bus_speed = ast_i2c_set_speed,
  286. .deblock = ast_i2c_deblock,
  287. };
  288. static const struct udevice_id ast_i2c_ids[] = {
  289. { .compatible = "aspeed,ast2400-i2c-bus" },
  290. { .compatible = "aspeed,ast2500-i2c-bus" },
  291. { .compatible = "aspeed,ast2600-i2c-bus" },
  292. { },
  293. };
  294. U_BOOT_DRIVER(ast_i2c) = {
  295. .name = "ast_i2c",
  296. .id = UCLASS_I2C,
  297. .of_match = ast_i2c_ids,
  298. .probe = ast_i2c_probe,
  299. .of_to_plat = ast_i2c_of_to_plat,
  300. .priv_auto = sizeof(struct ast_i2c_priv),
  301. .ops = &ast_i2c_ops,
  302. };