pinctrl-mxs.c 4.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2019 DENX Software Engineering
  4. * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
  5. */
  6. #include <common.h>
  7. #include <log.h>
  8. #include <asm/global_data.h>
  9. #include <dm/device_compat.h>
  10. #include <dm/devres.h>
  11. #include <linux/io.h>
  12. #include <linux/err.h>
  13. #include <dm.h>
  14. #include <dm/pinctrl.h>
  15. #include <dm/read.h>
  16. #include "pinctrl-mxs.h"
  17. DECLARE_GLOBAL_DATA_PTR;
  18. struct mxs_pinctrl_priv {
  19. void __iomem *base;
  20. const struct mxs_regs *regs;
  21. };
  22. static unsigned long mxs_dt_node_to_map(struct udevice *conf)
  23. {
  24. unsigned long config = 0;
  25. int ret;
  26. u32 val;
  27. ret = dev_read_u32(conf, "fsl,drive-strength", &val);
  28. if (!ret)
  29. config = val | MA_PRESENT;
  30. ret = dev_read_u32(conf, "fsl,voltage", &val);
  31. if (!ret)
  32. config |= val << VOL_SHIFT | VOL_PRESENT;
  33. ret = dev_read_u32(conf, "fsl,pull-up", &val);
  34. if (!ret)
  35. config |= val << PULL_SHIFT | PULL_PRESENT;
  36. return config;
  37. }
  38. static int mxs_pinctrl_set_mux(struct udevice *dev, u32 val, int bank, int pin)
  39. {
  40. struct mxs_pinctrl_priv *iomux = dev_get_priv(dev);
  41. int muxsel = MUXID_TO_MUXSEL(val), shift;
  42. void __iomem *reg;
  43. reg = iomux->base + iomux->regs->muxsel;
  44. reg += bank * 0x20 + pin / 16 * 0x10;
  45. shift = pin % 16 * 2;
  46. mxs_pinctrl_rmwl(muxsel, 0x3, shift, reg);
  47. debug(" mux %d,", muxsel);
  48. return 0;
  49. }
  50. static int mxs_pinctrl_set_state(struct udevice *dev, struct udevice *conf)
  51. {
  52. struct mxs_pinctrl_priv *iomux = dev_get_priv(dev);
  53. u32 *pin_data, val, ma, vol, pull;
  54. int npins, size, i, ret;
  55. unsigned long config;
  56. debug("\n%s: set state: %s\n", __func__, conf->name);
  57. size = dev_read_size(conf, "fsl,pinmux-ids");
  58. if (size < 0)
  59. return size;
  60. if (!size || size % sizeof(int)) {
  61. dev_err(dev, "Invalid fsl,pinmux-ids property in %s\n",
  62. conf->name);
  63. return -EINVAL;
  64. }
  65. npins = size / sizeof(int);
  66. pin_data = devm_kzalloc(dev, size, 0);
  67. if (!pin_data)
  68. return -ENOMEM;
  69. ret = dev_read_u32_array(conf, "fsl,pinmux-ids", pin_data, npins);
  70. if (ret) {
  71. dev_err(dev, "Error reading pin data.\n");
  72. devm_kfree(dev, pin_data);
  73. return -EINVAL;
  74. }
  75. config = mxs_dt_node_to_map(conf);
  76. ma = CFG_TO_MA(config);
  77. vol = CFG_TO_VOL(config);
  78. pull = CFG_TO_PULL(config);
  79. for (i = 0; i < npins; i++) {
  80. int pinid, bank, pin, shift;
  81. void __iomem *reg;
  82. val = pin_data[i];
  83. pinid = MUXID_TO_PINID(val);
  84. bank = PINID_TO_BANK(pinid);
  85. pin = PINID_TO_PIN(pinid);
  86. debug("(val: 0x%x) pin %d,", val, pinid);
  87. /* Setup pinmux */
  88. mxs_pinctrl_set_mux(dev, val, bank, pin);
  89. debug(" ma: %d, vol: %d, pull: %d\n", ma, vol, pull);
  90. /* drive */
  91. reg = iomux->base + iomux->regs->drive;
  92. reg += bank * 0x40 + pin / 8 * 0x10;
  93. /* mA */
  94. if (config & MA_PRESENT) {
  95. shift = pin % 8 * 4;
  96. mxs_pinctrl_rmwl(ma, 0x3, shift, reg);
  97. }
  98. /* vol */
  99. if (config & VOL_PRESENT) {
  100. shift = pin % 8 * 4 + 2;
  101. if (vol)
  102. writel(1 << shift, reg + SET);
  103. else
  104. writel(1 << shift, reg + CLR);
  105. }
  106. /* pull */
  107. if (config & PULL_PRESENT) {
  108. reg = iomux->base + iomux->regs->pull;
  109. reg += bank * 0x10;
  110. shift = pin;
  111. if (pull)
  112. writel(1 << shift, reg + SET);
  113. else
  114. writel(1 << shift, reg + CLR);
  115. }
  116. }
  117. devm_kfree(dev, pin_data);
  118. return 0;
  119. }
  120. static struct pinctrl_ops mxs_pinctrl_ops = {
  121. .set_state = mxs_pinctrl_set_state,
  122. };
  123. static int mxs_pinctrl_probe(struct udevice *dev)
  124. {
  125. struct mxs_pinctrl_priv *iomux = dev_get_priv(dev);
  126. iomux->base = dev_read_addr_ptr(dev);
  127. iomux->regs = (struct mxs_regs *)dev_get_driver_data(dev);
  128. return 0;
  129. }
  130. static const struct mxs_regs imx23_regs = {
  131. .muxsel = 0x100,
  132. .drive = 0x200,
  133. .pull = 0x400,
  134. };
  135. static const struct mxs_regs imx28_regs = {
  136. .muxsel = 0x100,
  137. .drive = 0x300,
  138. .pull = 0x600,
  139. };
  140. static const struct udevice_id mxs_pinctrl_match[] = {
  141. { .compatible = "fsl,imx23-pinctrl", .data = (ulong)&imx23_regs },
  142. { .compatible = "fsl,imx28-pinctrl", .data = (ulong)&imx28_regs },
  143. { /* sentinel */ }
  144. };
  145. U_BOOT_DRIVER(fsl_imx23_pinctrl) = {
  146. .name = "fsl_imx23_pinctrl",
  147. .id = UCLASS_PINCTRL,
  148. .of_match = of_match_ptr(mxs_pinctrl_match),
  149. .probe = mxs_pinctrl_probe,
  150. #if CONFIG_IS_ENABLED(OF_REAL)
  151. .bind = dm_scan_fdt_dev,
  152. #endif
  153. .priv_auto = sizeof(struct mxs_pinctrl_priv),
  154. .ops = &mxs_pinctrl_ops,
  155. };
  156. DM_DRIVER_ALIAS(fsl_imx23_pinctrl, fsl_imx28_pinctrl)