rockchip_timer.c 4.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017 Theobroma Systems Design und Consulting GmbH
  4. */
  5. #include <common.h>
  6. #include <bootstage.h>
  7. #include <dm.h>
  8. #include <init.h>
  9. #include <log.h>
  10. #include <asm/global_data.h>
  11. #include <dm/ofnode.h>
  12. #include <mapmem.h>
  13. #include <asm/arch-rockchip/timer.h>
  14. #include <dt-structs.h>
  15. #include <timer.h>
  16. #include <asm/io.h>
  17. DECLARE_GLOBAL_DATA_PTR;
  18. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  19. struct rockchip_timer_plat {
  20. struct dtd_rockchip_rk3288_timer dtd;
  21. };
  22. #endif
  23. /* Driver private data. Contains timer id. Could be either 0 or 1. */
  24. struct rockchip_timer_priv {
  25. struct rk_timer *timer;
  26. };
  27. static inline int64_t rockchip_timer_get_curr_value(struct rk_timer *timer)
  28. {
  29. uint64_t timebase_h, timebase_l;
  30. uint64_t cntr;
  31. timebase_l = readl(&timer->timer_curr_value0);
  32. timebase_h = readl(&timer->timer_curr_value1);
  33. cntr = timebase_h << 32 | timebase_l;
  34. return cntr;
  35. }
  36. #if CONFIG_IS_ENABLED(BOOTSTAGE)
  37. ulong timer_get_boot_us(void)
  38. {
  39. uint64_t ticks = 0;
  40. uint32_t rate;
  41. uint64_t us;
  42. int ret;
  43. ret = dm_timer_init();
  44. if (!ret) {
  45. /* The timer is available */
  46. rate = timer_get_rate(gd->timer);
  47. timer_get_count(gd->timer, &ticks);
  48. } else if (CONFIG_IS_ENABLED(OF_REAL) && ret == -EAGAIN) {
  49. /* We have been called so early that the DM is not ready,... */
  50. ofnode node = offset_to_ofnode(-1);
  51. struct rk_timer *timer = NULL;
  52. /*
  53. * ... so we try to access the raw timer, if it is specified
  54. * via the tick-timer property in /chosen.
  55. */
  56. node = ofnode_get_chosen_node("tick-timer");
  57. if (!ofnode_valid(node)) {
  58. debug("%s: no /chosen/tick-timer\n", __func__);
  59. return 0;
  60. }
  61. timer = (struct rk_timer *)ofnode_get_addr(node);
  62. /* This timer is down-counting */
  63. ticks = ~0uLL - rockchip_timer_get_curr_value(timer);
  64. if (ofnode_read_u32(node, "clock-frequency", &rate)) {
  65. debug("%s: could not read clock-frequency\n", __func__);
  66. return 0;
  67. }
  68. } else {
  69. return 0;
  70. }
  71. us = (ticks * 1000) / rate;
  72. return us;
  73. }
  74. #endif
  75. static u64 rockchip_timer_get_count(struct udevice *dev)
  76. {
  77. struct rockchip_timer_priv *priv = dev_get_priv(dev);
  78. uint64_t cntr = rockchip_timer_get_curr_value(priv->timer);
  79. /* timers are down-counting */
  80. return ~0ull - cntr;
  81. }
  82. static int rockchip_clk_of_to_plat(struct udevice *dev)
  83. {
  84. if (CONFIG_IS_ENABLED(OF_REAL)) {
  85. struct rockchip_timer_priv *priv = dev_get_priv(dev);
  86. priv->timer = dev_read_addr_ptr(dev);
  87. if (!priv->timer)
  88. return -ENOENT;
  89. }
  90. return 0;
  91. }
  92. static int rockchip_timer_start(struct udevice *dev)
  93. {
  94. struct rockchip_timer_priv *priv = dev_get_priv(dev);
  95. const uint64_t reload_val = ~0uLL;
  96. const uint32_t reload_val_l = reload_val & 0xffffffff;
  97. const uint32_t reload_val_h = reload_val >> 32;
  98. /* don't reinit, if the timer is already running and set up */
  99. if ((readl(&priv->timer->timer_ctrl_reg) & 1) == 1 &&
  100. (readl(&priv->timer->timer_load_count0) == reload_val_l) &&
  101. (readl(&priv->timer->timer_load_count1) == reload_val_h))
  102. return 0;
  103. /* disable timer and reset all control */
  104. writel(0, &priv->timer->timer_ctrl_reg);
  105. /* write reload value */
  106. writel(reload_val_l, &priv->timer->timer_load_count0);
  107. writel(reload_val_h, &priv->timer->timer_load_count1);
  108. /* enable timer */
  109. writel(1, &priv->timer->timer_ctrl_reg);
  110. return 0;
  111. }
  112. static int rockchip_timer_probe(struct udevice *dev)
  113. {
  114. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  115. struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
  116. struct rockchip_timer_priv *priv = dev_get_priv(dev);
  117. struct rockchip_timer_plat *plat = dev_get_plat(dev);
  118. priv->timer = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
  119. uc_priv->clock_rate = plat->dtd.clock_frequency;
  120. #endif
  121. return rockchip_timer_start(dev);
  122. }
  123. static const struct timer_ops rockchip_timer_ops = {
  124. .get_count = rockchip_timer_get_count,
  125. };
  126. static const struct udevice_id rockchip_timer_ids[] = {
  127. { .compatible = "rockchip,rk3288-timer" },
  128. {}
  129. };
  130. U_BOOT_DRIVER(rockchip_rk3288_timer) = {
  131. .name = "rockchip_rk3288_timer",
  132. .id = UCLASS_TIMER,
  133. .of_match = rockchip_timer_ids,
  134. .probe = rockchip_timer_probe,
  135. .ops = &rockchip_timer_ops,
  136. .priv_auto = sizeof(struct rockchip_timer_priv),
  137. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  138. .plat_auto = sizeof(struct rockchip_timer_plat),
  139. #endif
  140. .of_to_plat = rockchip_clk_of_to_plat,
  141. };