ark1668ed_fpga.dts 21 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /dts-v1/;
  3. /include/ "skeleton.dtsi"
  4. #include <dt-bindings/interrupt-controller/arm-gic.h>
  5. #include <dt-bindings/gpio/gpio.h>
  6. / {
  7. model = "ARM Arkmicro ark1668ed SoC";
  8. compatible = "arkmicro,ark1668e,ark1668ed";
  9. interrupt-parent = <&gic>;
  10. aliases {
  11. serial0 = &uart0;
  12. // hsserial0 = &uart4;
  13. // hsserial1 = &uart5;
  14. };
  15. chosen {
  16. bootargs = "console=ttyS0,115200 earlyprintk loglevel=8 clk_ignore_unused";
  17. stdout-path = "serial0:115200n8";
  18. };
  19. cpus {
  20. #address-cells = <1>;
  21. #size-cells = <0>;
  22. enable-method = "arkmicro,arke-smp";
  23. cpu0: cpu@0 {
  24. compatible = "arm,cortex-a7";
  25. device_type = "cpu";
  26. reg = <0>;
  27. clock-frequency = <24000000>;
  28. };
  29. cpu1: cpu@1 {
  30. compatible = "arm,cortex-a7";
  31. device_type = "cpu";
  32. reg = <1>;
  33. clock-frequency = <24000000>;
  34. };
  35. };
  36. memory {
  37. reg = <0x60000000 0x18000000>;
  38. };
  39. reserved-memory {
  40. #address-cells = <1>;
  41. #size-cells = <1>;
  42. ranges;
  43. /* global autoconfigured region for contiguous allocations */
  44. linux,cma {
  45. compatible = "shared-dma-pool";
  46. reusable;
  47. size = <0x8000000>;
  48. linux,cma-default;
  49. };
  50. };
  51. iram {
  52. compatible = "arkmicro,arke-iram";
  53. reg = <0x300000 0x8000>;
  54. cpuctlofset = <0x34>;
  55. enablebit = <0x0>;
  56. };
  57. timer {
  58. compatible = "arm,armv7-timer";
  59. arm,cpu-registers-not-fw-configured;
  60. interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  61. <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  62. <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  63. <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  64. clock-frequency = <24000000>;
  65. };
  66. sregs@50000000 {
  67. compatible = "arkmicro,ark-sregs";
  68. reg = <0x50000000 0x1000>;
  69. clocks {
  70. #address-cells = <1>;
  71. #size-cells = <0>;
  72. /* cpu axi ahb apb */
  73. clk24mhz: clk24mhz@24M {
  74. #clock-cells = <0>;
  75. compatible = "fixed-clock";
  76. clock-frequency = <24000000>;
  77. };
  78. /* ddr */
  79. clk100mhz: clk100mhz@20M {
  80. #clock-cells = <0>;
  81. compatible = "fixed-clock";
  82. clock-frequency = <100000000>;
  83. };
  84. /* lcd */
  85. clk15mhz: clk15mhz@15M {
  86. #clock-cells = <0>;
  87. compatible = "fixed-clock";
  88. clock-frequency = <15000000>;
  89. };
  90. /* peripheral */
  91. clk12mhz: clk12mhz@12M {
  92. #clock-cells = <0>;
  93. compatible = "fixed-clock";
  94. clock-frequency = <24000000>;
  95. };
  96. clk30mhz: clk30mhz@30M {
  97. #clock-cells = <0>;
  98. compatible = "fixed-clock";
  99. clock-frequency = <30000000>;
  100. };
  101. eth_phy_ref_clk: eth_phy_ref_clk {
  102. #clock-cells = <0>;
  103. compatible = "fixed-clock";
  104. clock-frequency = <25000000>;
  105. };
  106. wm8960_mclk: wm8960_mclk {
  107. #clock-cells = <0>;
  108. compatible = "fixed-clock";
  109. clock-frequency = <12288000>;
  110. };
  111. i2s_dac_clk: i2s_dac_clk {
  112. #clock-cells = <0>;
  113. compatible = "fixed-clock";
  114. clock-frequency = <48000>;
  115. };
  116. i2s_adc_clk: i2s_adc_clk {
  117. #clock-cells = <0>;
  118. compatible = "fixed-clock";
  119. clock-frequency = <48000>;
  120. };
  121. };
  122. };
  123. soc {
  124. compatible = "simple-bus";
  125. #address-cells = <1>;
  126. #size-cells = <1>;
  127. ranges;
  128. gic: interrupt-controller@e0b01000 {
  129. compatible = "arm,cortex-a7-gic";
  130. interrupt-controller;
  131. #interrupt-cells = <3>;
  132. reg = <0xe0b01000 0x1000>,
  133. <0xe0b02000 0x2000>,
  134. <0xe0b04000 0x2000>,
  135. <0xe0b06000 0x2000>;
  136. //interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  137. };
  138. pinctrl0: pinctrl@50000000 {
  139. compatible = "arkmicro,ark1668ed-pinctrl";
  140. reg = <0x50000000 0x1000>;
  141. };
  142. // dmac: dmac@40200000 {
  143. // compatible = "snps,axi-dma-1.01a";
  144. // reg = <0x40200000 0x1000>;
  145. // interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
  146. // clocks = <&clk24mhz>, <&clk24mhz>;
  147. // clock-names = "core-clk", "cfgr-clk";
  148. // #dma-cells = <3>;
  149. // dma-channels = <8>;
  150. // snps,dma-masters = <2>;
  151. // snps,data-width = <3>;
  152. // snps,block-size = <65536 65536 65536 65536
  153. // 65536 65536 65536 65536>;
  154. // snps,priority = <0 1 2 3 4 5 6 7>;
  155. // snps,axi-max-burst-len = <16>;
  156. // status = "disabled";
  157. // };
  158. #if 0
  159. dmac: dmac@40200000 {
  160. compatible = "arm,pl080", "arm,primecell";
  161. reg = <0x40200000 0x1000>;
  162. // interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
  163. interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
  164. // clocks = <&clk LPC32XX_CLK_DMA>;
  165. clocks = <&clk24mhz>;
  166. clock-names = "apb_pclk";
  167. lli-bus-interface-ahb1;
  168. lli-bus-interface-ahb2;
  169. mem-bus-interface-ahb2;
  170. memcpy-burst-size = <256>;
  171. memcpy-bus-width = <32>;
  172. #dma-cells = <3>;
  173. //status = "disabled";
  174. };
  175. #else
  176. dmac: dmac@40200000 {
  177. compatible = "arkmicro,ark-dma";
  178. reg = <0x40200000 0x1000>;
  179. interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
  180. dma-channels = <8>;
  181. dma-masters = <2>;
  182. chan_allocation_order = <1>;
  183. chan_priority = <1>;
  184. block_size = <0xfff>;
  185. data-width = <4 4>;
  186. /* multi-block = <1 1 1 1 1 1 1 1>; */
  187. clocks = <&clk24mhz>;
  188. clock-names = "hclk";
  189. lli-bus-interface-ahb1;
  190. lli-bus-interface-ahb2;
  191. mem-bus-interface-ahb2;
  192. #dma-cells = <3>;
  193. };
  194. #endif
  195. i2s_adc: i2s-adc@50100000 {
  196. compatible = "arkmicro,ark1668e-i2s";
  197. reg = <0x50100000 0x1000
  198. 0x50000000 0x1000>;
  199. interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
  200. nco-reg = <0x4040815c>;
  201. dmas = <&dmac 0 1 0>, <&dmac 1 0 1>;
  202. dma-names = "rx", "tx";
  203. clocks = <&i2s_adc_clk>;
  204. // pinctrl-0 = <&pinctrl_i2sadc_sync &pinctrl_i2sadc_sadata
  205. // &pinctrl_i2sadc_mclk &pinctrl_i2sadc_bclk>;
  206. // pinctrl-names = "default";
  207. #sound-dai-cells = <0>;
  208. status = "disabled";
  209. };
  210. i2s_dac: i2s-dac@50d00000 {
  211. compatible = "arkmicro,ark1668e-i2s";
  212. reg = <0x50d00000 0x1000
  213. 0x50000000 0x1000>;
  214. interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
  215. nco-reg = <0x4040816c>;
  216. dmas = <&dmac 25 1 0>, <&dmac 26 0 1>;
  217. dma-names = "rx", "tx";
  218. clocks = <&i2s_dac_clk>;
  219. // pinctrl-0 = <&pinctrl_i2sdac_sync &pinctrl_i2sdac_sadata
  220. // &pinctrl_i2sdac_mclk &pinctrl_i2sdac_bclk>;
  221. // pinctrl-names = "default";
  222. #sound-dai-cells = <0>;
  223. status = "disabled";
  224. };
  225. uart0: uart@50500000 {
  226. compatible = "snps,dw-apb-uart";
  227. reg = <0x50500000 0x1000>;
  228. interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
  229. clocks = <&clk24mhz>;
  230. reg-shift = <2>;
  231. pinctrl-names = "default";
  232. pinctrl-0 = <&pinctrl_uart0>;
  233. //dmas = <&dmac 6 1 0>, <&dmac 7 0 1>;
  234. //dma-names = "rx", "tx";
  235. };
  236. uart1: uart@50600000 {
  237. compatible = "snps,dw-apb-uart";
  238. reg = <0x50600000 0x1000>;
  239. interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
  240. current-speed = <115200>;
  241. clocks = <&clk12mhz>;
  242. pinctrl-names = "default";
  243. pinctrl-0 = <&pinctrl_uart1>;
  244. //dmas = <&dmac 12 1 0>, <&dmac 13 0 1>;
  245. //dma-names = "rx", "tx";
  246. //status = "disabled";
  247. };
  248. uart2: uart@50700000 {
  249. compatible = "snps,dw-apb-uart";
  250. reg = <0x50700000 0x1000>;
  251. interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
  252. current-speed = <115200>;
  253. clocks = <&clk12mhz>;
  254. pinctrl-names = "default";
  255. pinctrl-0 = <&pinctrl_uart2>;
  256. //dmas = <&dmac 19 1 0>, <&dmac 20 0 1>;
  257. //dma-names = "rx", "tx";
  258. //status = "disabled";
  259. };
  260. uart3: uart@50800000 {
  261. //compatible = "arkmicro,ark-uart";
  262. compatible = "snps,dw-apb-uart";
  263. reg = <0x50800000 0x1000>;
  264. interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
  265. current-speed = <115200>;
  266. pinctrl-names = "default";
  267. pinctrl-0 = <&pinctrl_uart3>;
  268. clocks = <&clk12mhz>;
  269. //dmas = <&dmac 21 1 0>, <&dmac 22 0 1>;
  270. //dma-names = "rx", "tx";
  271. //status = "disabled";
  272. };
  273. uart4: uart@51300000 {
  274. //compatible = "arkmicro,ark-uart";
  275. compatible = "snps,dw-apb-uart";
  276. reg = <0x51300000 0x4000>;
  277. interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
  278. clocks = <&clk12mhz>;
  279. //pinctrl-names = "default";
  280. //pinctrl-0 = <&pinctrl_uart4>;
  281. dmas = <&dmac 14 1 0>, <&dmac 15 0 1>;
  282. dma-names = "rx", "tx";
  283. status = "disabled";
  284. };
  285. uart5: uart@51d00000 {
  286. //compatible = "arkmicro,ark-uart";
  287. compatible = "snps,dw-apb-uart";
  288. reg = <0x51d00000 0x4000>;
  289. interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
  290. clocks = <&clk12mhz>;
  291. //pinctrl-names = "default";
  292. //pinctrl-0 = <&pinctrl_uart5>;
  293. dmas = <&dmac 16 1 0>, <&dmac 17 0 1>;
  294. dma-names = "rx", "tx";
  295. status = "disabled";
  296. };
  297. timer: timer@50a00000 {
  298. compatible = "snps,dw-apb-timer-osc";
  299. reg = <0x50a00000 0x1000>;
  300. interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
  301. clocks = <&clk12mhz>, <&clk24mhz>;
  302. clock-names = "timer", "pclk";
  303. };
  304. watchdog: watchdog@50c00000 {
  305. compatible = "arkmicro,ark-wdt";
  306. reg = <0x50c00000 0x20>;
  307. interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
  308. clocks = <&clk24mhz>;
  309. status = "disabled";
  310. };
  311. gpio0: gpio@50900000 {
  312. #address-cells = <1>;
  313. #size-cells = <0>;
  314. compatible = "snps,dw-apb-gpio";
  315. reg = <0x50900000 0x80>;
  316. // status = "disabled";
  317. gporta: gpio-controller@0 {
  318. compatible = "snps,dw-apb-gpio-port";
  319. gpio-controller;
  320. #gpio-cells = <2>;
  321. snps,nr-gpios = <32>;
  322. reg = <0>;
  323. base = <0>;
  324. interrupt-controller;
  325. #interrupt-cells = <2>;
  326. interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
  327. gpio-ranges = <&pinctrl0 0 0 32>;
  328. };
  329. };
  330. gpio1: gpio@50900080 {
  331. #address-cells = <1>;
  332. #size-cells = <0>;
  333. compatible = "snps,dw-apb-gpio";
  334. reg = <0x50900080 0x80>;
  335. // status = "disabled";
  336. gportb: gpio-controller@0 {
  337. compatible = "snps,dw-apb-gpio-port";
  338. gpio-controller;
  339. #gpio-cells = <2>;
  340. snps,nr-gpios = <32>;
  341. reg = <0>;
  342. base = <32>;
  343. interrupt-controller;
  344. #interrupt-cells = <2>;
  345. interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
  346. gpio-ranges = <&pinctrl0 0 32 32>;
  347. };
  348. };
  349. gpio2: gpio@50900100 {
  350. #address-cells = <1>;
  351. #size-cells = <0>;
  352. compatible = "snps,dw-apb-gpio";
  353. reg = <0x50900100 0x80>;
  354. // status = "disabled";
  355. gportc: gpio-controller@0 {
  356. compatible = "snps,dw-apb-gpio-port";
  357. gpio-controller;
  358. #gpio-cells = <2>;
  359. snps,nr-gpios = <32>;
  360. reg = <0>;
  361. base = <64>;
  362. interrupt-controller;
  363. #interrupt-cells = <2>;
  364. interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
  365. gpio-ranges = <&pinctrl0 0 64 32>;
  366. };
  367. };
  368. gpio3: gpio@50900180 {
  369. #address-cells = <1>;
  370. #size-cells = <0>;
  371. compatible = "snps,dw-apb-gpio";
  372. reg = <0x50900180 0x80>;
  373. // status = "disabled";
  374. gportd: gpio-controller@0 {
  375. compatible = "snps,dw-apb-gpio-port";
  376. gpio-controller;
  377. #gpio-cells = <2>;
  378. snps,nr-gpios = <32>;
  379. reg = <0>;
  380. base = <96>;
  381. interrupt-controller;
  382. #interrupt-cells = <2>;
  383. interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
  384. gpio-ranges = <&pinctrl0 0 96 32>;
  385. };
  386. };
  387. gpio4: gpio@50900200 {
  388. #address-cells = <1>;
  389. #size-cells = <0>;
  390. compatible = "snps,dw-apb-gpio";
  391. reg = <0x50900200 0x80>;
  392. // status = "disabled";
  393. gporte: gpio-controller@0 {
  394. compatible = "snps,dw-apb-gpio-port";
  395. gpio-controller;
  396. #gpio-cells = <2>;
  397. snps,nr-gpios = <32>;
  398. reg = <0>;
  399. base = <128>;
  400. interrupt-controller;
  401. #interrupt-cells = <2>;
  402. interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
  403. gpio-ranges = <&pinctrl0 0 128 32>;
  404. };
  405. };
  406. pwm0: pwm@50b00000 {
  407. compatible = "arkmicro,ark-pwm";
  408. reg = <0x50b00000 0x100>;
  409. #pwm-cells = <2>;
  410. pinctrl-names = "default";
  411. pinctrl-0 = <&pinctrl_pwm0 &pinctrl_pwm1 &pinctrl_pwm2
  412. &pinctrl_pwm3 &pinctrl_pwm4 &pinctrl_pwm5>;
  413. clocks = <&clk12mhz>;
  414. status = "disabled";
  415. };
  416. nfc: nand@20000000 {
  417. compatible = "arkmicro,ark-nand";
  418. reg = <0x20000000 0x1000>;
  419. max-chips = <1>;
  420. interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
  421. nand-bus-width = <8>;
  422. // nand-ecc-mode = "hw_syndrome";
  423. nand-ecc-mode = "hw";
  424. nand-ecc-placement = "oob";
  425. status = "disabled";
  426. };
  427. mmc0: mmc@40100000 {
  428. compatible = "snps,dw-mshc";
  429. #address-cells = <1>;
  430. #size-cells = <0>;
  431. reg = <0x40100000 0x1000>;
  432. interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
  433. fifo-depth = <64>;
  434. bus-width = <8>;
  435. cap-mmc-highspeed;
  436. disable-wp;
  437. non-removable;
  438. clocks = <&clk12mhz>;
  439. clock-names = "ciu";
  440. status = "disabled";
  441. };
  442. mmc1: mmc@40400000 {
  443. compatible = "snps,dw-mshc";
  444. #address-cells = <1>;
  445. #size-cells = <0>;
  446. reg = <0x40400000 0x1000>;
  447. interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
  448. //fifo-depth = <128>;
  449. fifo-depth = <64>;
  450. bus-width = <4>;
  451. //clocks = <&clk12mhz>;
  452. clock-frequency= <24000000>;
  453. clock-names = "ciu";
  454. //status = "disabled";
  455. };
  456. i2c0: i2c@50300000 {
  457. #address-cells = <1>;
  458. #size-cells = <0>;
  459. compatible = "snps,designware-i2c";
  460. reg = <0x50300000 0x1000>;
  461. interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
  462. pinctrl-names = "default";
  463. pinctrl-0 = <&pinctrl_i2c0>;
  464. clocks = <&clk24mhz>;
  465. clock-frequency = <400000>;
  466. eeprom0: eeprom@50 {
  467. compatible = "atmel,24c32";
  468. reg = <0x50>;
  469. pagesize = <32>;
  470. };
  471. };
  472. i2c1: i2c@50400000 {
  473. #address-cells = <1>;
  474. #size-cells = <0>;
  475. compatible = "snps,designware-i2c";
  476. reg = <0x50400000 0x1000>;
  477. interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
  478. pinctrl-names = "default";
  479. pinctrl-0 = <&pinctrl_i2c1>;
  480. clocks = <&clk12mhz>;
  481. status = "disabled";
  482. };
  483. i2c-gpio-0 {
  484. #address-cells = <1>;
  485. #size-cells = <0>;
  486. compatible = "i2c-gpio";
  487. gpios = <&gporte 15 0 /* SDA */
  488. &gporte 14 0 /* SCL */
  489. >;
  490. i2c-gpio,delay-us = <2>; /* clk freq = 500/delay KHz */
  491. i2c-gpio,scl-output-only;
  492. //i2c-gpio,sda-open-drain;
  493. //i2c-gpio,scl-open-drain;
  494. status = "disabled";
  495. codec: wm8960@1a {
  496. compatible = "wlf,wm8960";
  497. reg = <0x1a>;
  498. clocks = <&wm8960_mclk>;
  499. clock-names = "mclk";
  500. //wlf,shared-lrclk;
  501. #sound-dai-cells = <0>;
  502. };
  503. };
  504. ecspi: spi@50200000 {
  505. #address-cells = <1>;
  506. #size-cells = <0>;
  507. compatible = "arkmicro,arke-ecspi";
  508. reg = <0x50200000 0x1000>;
  509. num-chipselect = <1>;
  510. chipselects = <101>;
  511. interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
  512. //dmas = <&dmac 8 1 0>; //<&dmac 9 0 1>
  513. //dma-names = "rx"; //"tx"
  514. //pinctrl-names = "default";
  515. //pinctrl-0 = <&pinctrl_ecspi>;
  516. clocks = <&clk12mhz>, <&clk12mhz>;
  517. clock-names = "ipg", "per";
  518. status = "disabled";
  519. m25p80@0 {
  520. #address-cells = <1>;
  521. #size-cells = <1>;
  522. compatible = "w25q256";
  523. reg = <0>; /* Chip select 0 */
  524. spi-max-frequency = <3000000>;
  525. status = "disabled";
  526. };
  527. gd5f@0 {
  528. #address-cells = <1>;
  529. #size-cells = <1>;
  530. compatible = "gd5f";
  531. reg = <0>; /* Chip select 0 */
  532. spi-max-frequency = <3000000>;
  533. status = "disabled";
  534. };
  535. };
  536. dwssi: spi@30000000 {
  537. //compatible = "arkmicro,ark-dw-ssi";
  538. //compatible = "snps,dw-apb-ssi";
  539. compatible = "snps,dwc-ssi-1.01a";
  540. #address-cells = <1>;
  541. #size-cells = <0>;
  542. reg = <0x30000000 0x100>;
  543. interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
  544. num-cs = <1>;
  545. //cs-gpios = <&gportd 14 0>;
  546. // dmas = <&dmac 0 1 0>, <&dmac 1 0 1>;
  547. // dma-names = "rx", "tx";
  548. // pinctrl-names = "default";
  549. // pinctrl-0 = <&pinctrl_dwssi_0>;
  550. clocks = <&clk24mhz>;
  551. //reg-io-width = <1>;
  552. status = "disabled";
  553. m25p80@0 {
  554. #address-cells = <1>;
  555. #size-cells = <1>;
  556. compatible = "w25q256";
  557. reg = <0>; /* Chip select 0 */
  558. spi-max-frequency = <3000000>;
  559. //spi-tx-bus-width = <1>;
  560. //spi-rx-bus-width = <4>;
  561. //status = "disabled";
  562. };
  563. gd5f@0 {
  564. #address-cells = <1>;
  565. #size-cells = <1>;
  566. compatible = "gd5f";
  567. reg = <0>; /* Chip select 0 */
  568. spi-max-frequency = <3000000>;
  569. status = "disabled";
  570. };
  571. };
  572. gpu0: gpu@40600000 {
  573. compatible = "arkmicro,ark1668ed_gc555";
  574. // reg = <0x40600000 0x1000
  575. // 0x7A000000 0x500000>;
  576. interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
  577. clocks = <&clk24mhz>;
  578. // clock-names = "gpu0_clk";
  579. };
  580. vdec0: vdec@40700000 {
  581. compatible = "on2,ark-vdec";
  582. reg = <0x40700000 0x1000
  583. 0x7e000000 0x500000>;
  584. interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
  585. clocks = <&clk24mhz>;
  586. clock-names = "vdec_clk";
  587. };
  588. ethernet: ethernet@40b00000 {
  589. compatible = "snps,dwc-qos-ethernet-4.10";
  590. reg = <0x40b00000 0x4000>;
  591. interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
  592. snps,write-requests = <2>;
  593. snps,read-requests = <16>;
  594. snps,txpbl = <8>;
  595. snps,rxpbl = <2>;
  596. snps,reset-gpio = <&gportd 15 GPIO_ACTIVE_LOW>;
  597. snps,reset-active-low;
  598. snps,reset-delays-us = <0 10000 1000000>;
  599. clocks = <&eth_phy_ref_clk>, <&eth_phy_ref_clk>;
  600. clock-names = "phy_ref_clk", "apb_pclk";
  601. // status = "disabled";
  602. phy-handle = <&phy1>;
  603. phy-mode = "rgmii";
  604. mdio {
  605. #address-cells = <0x1>;
  606. #size-cells = <0x0>;
  607. phy1: phy@0 {
  608. compatible = "ethernet-phy-ieee802.3-c22";
  609. device_type = "ethernet-phy";
  610. reg = <0x5>;
  611. };
  612. };
  613. };
  614. #if 0
  615. gpu@40500000 {
  616. compatible = "arm,mali-400", "arm,mali-utgard";
  617. reg = <0x40500000 0x30000>;
  618. interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
  619. <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
  620. <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
  621. <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
  622. <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
  623. <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
  624. <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
  625. interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1";
  626. //pmu_domain_config = <0x1 0x4 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x2 0x0 0x0>;
  627. //pmu_switch_delay = <0xff>;
  628. clocks = <&clk24mhz>, <&clk24mhz>;
  629. clock-names = "mali_parent", "mali";
  630. status = "disabled";
  631. };
  632. #endif
  633. lcdc: lcd@40300000 {
  634. compatible = "arkmicro,ark1668e-lcdc";
  635. reg = <0x40300000 0x1000
  636. 0x7F000000 0x1000000>;
  637. interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
  638. clocks = <&clk24mhz>;
  639. clock-names = "lcdc_clk";
  640. display = <&display0>;
  641. pinctrl-names = "default";
  642. pinctrl-0 = <&pinctrl_lcd_rgb888>;
  643. display0: display@0 {
  644. interface-type = "TTL";
  645. bits-per-pixel = <32>;
  646. //power-control-gpio = <&gpio2 17 GPIO_ACTIVE_HIGH>;
  647. lcd-wiring-mode = "RGB";
  648. //lcdcon-backlight;
  649. //pwms = <&pwm0 1 50000>;
  650. //pwm-names = "backlight";
  651. //backlight-value = <20>;
  652. //backlight-delay = <200>;
  653. display-timings {
  654. native-mode = <&timing0>;
  655. timing0: timing0 {
  656. clock-frequency = <24000000>;
  657. hactive = <1024>;
  658. vactive = <600>;
  659. hback-porch = <64>;
  660. hfront-porch = <21>;
  661. vback-porch = <16>;
  662. vfront-porch = <24>;
  663. hsync-len = <21>;
  664. vsync-len = <80>;
  665. hsync-active = <1>;
  666. vsync-active = <1>;
  667. de-active = <0>;
  668. pixelclk-active = <0>;
  669. };
  670. };
  671. };
  672. };
  673. #if 0
  674. usb0_phy: usb0-phy {
  675. compatible = "usb-nop-xceiv";
  676. #phy-cells = <0>;
  677. // status = "disabled";
  678. };
  679. usb0: usb@40000000 {
  680. compatible = "snps,dwc2";
  681. #address-cells = <1>;
  682. #size-cells = <0>;
  683. reg = <0x40000000 0x40000>;
  684. interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
  685. phys = <&usb0_phy>;
  686. phy-names = "usb0-phy";
  687. dr_mode = "host";
  688. // status = "disabled";
  689. };
  690. #endif
  691. usb1_phy: usb1-phy {
  692. compatible = "usb-nop-xceiv";
  693. #phy-cells = <0>;
  694. // status = "disabled";
  695. };
  696. usb1: usb@40C00000 {
  697. compatible = "snps,dwc2";
  698. #address-cells = <1>;
  699. #size-cells = <0>;
  700. reg = <0x40C00000 0x40000>;
  701. interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
  702. phys = <&usb1_phy>;
  703. phy-names = "usb1-phy";
  704. dr_mode = "host";
  705. // status = "disabled";
  706. };
  707. };
  708. sound {
  709. compatible = "simple-audio-card";
  710. simple-audio-card,name = "ark1668e fpga audio";
  711. simple-audio-card,widgets =
  712. "Microphone", "Mic Jack",
  713. "Line", "Line In",
  714. "Headphone", "Headphone Jack";
  715. simple-audio-card,routing =
  716. "Headphone Jack", "HP_L",
  717. "Headphone Jack", "HP_R",
  718. "LINPUT1", "Mic Jack",
  719. "LINPUT2", "Mic Jack",
  720. "RINPUT1", "Mic Jack",
  721. "RINPUT2", "Mic Jack";
  722. status = "disabled";
  723. simple-audio-card,dai-link@0 { /* I2S - adc */
  724. format = "i2s";
  725. bitclock-master = <&capture_codec>;
  726. frame-master = <&capture_codec>;
  727. capture_cpu: cpu {
  728. sound-dai = <&i2s_adc>;
  729. };
  730. capture_codec: codec {
  731. sound-dai = <&codec>;
  732. };
  733. };
  734. simple-audio-card,dai-link@1 { /* I2S - dac */
  735. format = "i2s";
  736. bitclock-master = <&playback_codec>;
  737. frame-master = <&playback_codec>;
  738. playback_cpu: cpu {
  739. sound-dai = <&i2s_dac>;
  740. };
  741. playback_codec: codec {
  742. sound-dai = <&codec>;
  743. };
  744. };
  745. };
  746. axi_scale: axi-scale@41000000 {
  747. compatible = "arkmicro,ark1668ed-axi-scale";
  748. reg = <0x41000000 0x1000
  749. 0x50000000 0x1000>;
  750. interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
  751. clocks = <&clk24mhz>;
  752. /* softreset-reg = <0x74>;
  753. softreset-offset = <28>;
  754. */
  755. };
  756. /* ituin: ituin@e0800000 {
  757. compatible = "arkmicro,ark1668ed-vin";
  758. reg = <0xe0800000 0x1000
  759. 0xe4900000 0x1000
  760. 0xe0a00000 0x1000
  761. 0xe0500000 0x1000>;
  762. interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
  763. pinctrl-0 = <&pinctrl_hvsync &pinctrl_itu0>;
  764. pinctrl-1 = <&pinctrl_hvsync &pinctrl_itu1>;
  765. pinctrl-2 = <&pinctrl_hvsync &pinctrl_itu2>;
  766. pinctrl-names = "itu0", "itu1", "itu2";
  767. status = "disabled";
  768. port {
  769. #address-cells = <1>;
  770. #size-cells = <0>;
  771. };
  772. };
  773. */
  774. /* carback: carback@0 {
  775. compatible = "arkmicro,ark-carback";
  776. interrupt-parent = <&gportf>;
  777. interrupts = <25 IRQ_TYPE_EDGE_BOTH>;
  778. detect-gpios = <&gportf 25 GPIO_ACTIVE_HIGH>;
  779. debounce-detect = <20>;
  780. status = "disabled";
  781. };
  782. */
  783. };
  784. #include "ark1668ed-pinctrl.dtsi"