pcieaer-howto.rst 9.3 KB

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  1. .. SPDX-License-Identifier: GPL-2.0
  2. .. include:: <isonum.txt>
  3. ===========================================================
  4. The PCI Express Advanced Error Reporting Driver Guide HOWTO
  5. ===========================================================
  6. :Authors: - T. Long Nguyen <tom.l.nguyen@intel.com>
  7. - Yanmin Zhang <yanmin.zhang@intel.com>
  8. :Copyright: |copy| 2006 Intel Corporation
  9. Overview
  10. ===========
  11. About this guide
  12. ----------------
  13. This guide describes the basics of the PCI Express (PCIe) Advanced Error
  14. Reporting (AER) driver and provides information on how to use it, as
  15. well as how to enable the drivers of Endpoint devices to conform with
  16. the PCIe AER driver.
  17. What is the PCIe AER Driver?
  18. ----------------------------
  19. PCIe error signaling can occur on the PCIe link itself
  20. or on behalf of transactions initiated on the link. PCIe
  21. defines two error reporting paradigms: the baseline capability and
  22. the Advanced Error Reporting capability. The baseline capability is
  23. required of all PCIe components providing a minimum defined
  24. set of error reporting requirements. Advanced Error Reporting
  25. capability is implemented with a PCIe Advanced Error Reporting
  26. extended capability structure providing more robust error reporting.
  27. The PCIe AER driver provides the infrastructure to support PCIe Advanced
  28. Error Reporting capability. The PCIe AER driver provides three basic
  29. functions:
  30. - Gathers the comprehensive error information if errors occurred.
  31. - Reports error to the users.
  32. - Performs error recovery actions.
  33. The AER driver only attaches to Root Ports and RCECs that support the PCIe
  34. AER capability.
  35. User Guide
  36. ==========
  37. Include the PCIe AER Root Driver into the Linux Kernel
  38. ------------------------------------------------------
  39. The PCIe AER driver is a Root Port service driver attached
  40. via the PCIe Port Bus driver. If a user wants to use it, the driver
  41. must be compiled. It is enabled with CONFIG_PCIEAER, which
  42. depends on CONFIG_PCIEPORTBUS.
  43. Load PCIe AER Root Driver
  44. -------------------------
  45. Some systems have AER support in firmware. Enabling Linux AER support at
  46. the same time the firmware handles AER would result in unpredictable
  47. behavior. Therefore, Linux does not handle AER events unless the firmware
  48. grants AER control to the OS via the ACPI _OSC method. See the PCI Firmware
  49. Specification for details regarding _OSC usage.
  50. AER error output
  51. ----------------
  52. When a PCIe AER error is captured, an error message will be output to
  53. console. If it's a correctable error, it is output as an info message.
  54. Otherwise, it is printed as an error. So users could choose different
  55. log level to filter out correctable error messages.
  56. Below shows an example::
  57. 0000:50:00.0: PCIe Bus Error: severity=Uncorrected (Fatal), type=Transaction Layer, id=0500(Requester ID)
  58. 0000:50:00.0: device [8086:0329] error status/mask=00100000/00000000
  59. 0000:50:00.0: [20] Unsupported Request (First)
  60. 0000:50:00.0: TLP Header: 04000001 00200a03 05010000 00050100
  61. In the example, 'Requester ID' means the ID of the device that sent
  62. the error message to the Root Port. Please refer to PCIe specs for other
  63. fields.
  64. AER Statistics / Counters
  65. -------------------------
  66. When PCIe AER errors are captured, the counters / statistics are also exposed
  67. in the form of sysfs attributes which are documented at
  68. Documentation/ABI/testing/sysfs-bus-pci-devices-aer_stats
  69. Developer Guide
  70. ===============
  71. To enable error recovery, a software driver must provide callbacks.
  72. To support AER better, developers need to understand how AER works.
  73. PCIe errors are classified into two types: correctable errors
  74. and uncorrectable errors. This classification is based on the impact
  75. of those errors, which may result in degraded performance or function
  76. failure.
  77. Correctable errors pose no impacts on the functionality of the
  78. interface. The PCIe protocol can recover without any software
  79. intervention or any loss of data. These errors are detected and
  80. corrected by hardware.
  81. Unlike correctable errors, uncorrectable
  82. errors impact functionality of the interface. Uncorrectable errors
  83. can cause a particular transaction or a particular PCIe link
  84. to be unreliable. Depending on those error conditions, uncorrectable
  85. errors are further classified into non-fatal errors and fatal errors.
  86. Non-fatal errors cause the particular transaction to be unreliable,
  87. but the PCIe link itself is fully functional. Fatal errors, on
  88. the other hand, cause the link to be unreliable.
  89. When PCIe error reporting is enabled, a device will automatically send an
  90. error message to the Root Port above it when it captures
  91. an error. The Root Port, upon receiving an error reporting message,
  92. internally processes and logs the error message in its AER
  93. Capability structure. Error information being logged includes storing
  94. the error reporting agent's requestor ID into the Error Source
  95. Identification Registers and setting the error bits of the Root Error
  96. Status Register accordingly. If AER error reporting is enabled in the Root
  97. Error Command Register, the Root Port generates an interrupt when an
  98. error is detected.
  99. Note that the errors as described above are related to the PCIe
  100. hierarchy and links. These errors do not include any device specific
  101. errors because device specific errors will still get sent directly to
  102. the device driver.
  103. Provide callbacks
  104. -----------------
  105. callback reset_link to reset PCIe link
  106. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  107. This callback is used to reset the PCIe physical link when a
  108. fatal error happens. The Root Port AER service driver provides a
  109. default reset_link function, but different Upstream Ports might
  110. have different specifications to reset the PCIe link, so
  111. Upstream Port drivers may provide their own reset_link functions.
  112. Section 3.2.2.2 provides more detailed info on when to call
  113. reset_link.
  114. PCI error-recovery callbacks
  115. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  116. The PCIe AER Root driver uses error callbacks to coordinate
  117. with downstream device drivers associated with a hierarchy in question
  118. when performing error recovery actions.
  119. Data struct pci_driver has a pointer, err_handler, to point to
  120. pci_error_handlers who consists of a couple of callback function
  121. pointers. The AER driver follows the rules defined in
  122. pci-error-recovery.rst except PCIe-specific parts (e.g.
  123. reset_link). Please refer to pci-error-recovery.rst for detailed
  124. definitions of the callbacks.
  125. The sections below specify when to call the error callback functions.
  126. Correctable errors
  127. ~~~~~~~~~~~~~~~~~~
  128. Correctable errors pose no impacts on the functionality of
  129. the interface. The PCIe protocol can recover without any
  130. software intervention or any loss of data. These errors do not
  131. require any recovery actions. The AER driver clears the device's
  132. correctable error status register accordingly and logs these errors.
  133. Non-correctable (non-fatal and fatal) errors
  134. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  135. If an error message indicates a non-fatal error, performing link reset
  136. at upstream is not required. The AER driver calls error_detected(dev,
  137. pci_channel_io_normal) to all drivers associated within a hierarchy in
  138. question. For example::
  139. Endpoint <==> Downstream Port B <==> Upstream Port A <==> Root Port
  140. If Upstream Port A captures an AER error, the hierarchy consists of
  141. Downstream Port B and Endpoint.
  142. A driver may return PCI_ERS_RESULT_CAN_RECOVER,
  143. PCI_ERS_RESULT_DISCONNECT, or PCI_ERS_RESULT_NEED_RESET, depending on
  144. whether it can recover or the AER driver calls mmio_enabled as next.
  145. If an error message indicates a fatal error, kernel will broadcast
  146. error_detected(dev, pci_channel_io_frozen) to all drivers within
  147. a hierarchy in question. Then, performing link reset at upstream is
  148. necessary. As different kinds of devices might use different approaches
  149. to reset link, AER port service driver is required to provide the
  150. function to reset link via callback parameter of pcie_do_recovery()
  151. function. If reset_link is not NULL, recovery function will use it
  152. to reset the link. If error_detected returns PCI_ERS_RESULT_CAN_RECOVER
  153. and reset_link returns PCI_ERS_RESULT_RECOVERED, the error handling goes
  154. to mmio_enabled.
  155. Frequent Asked Questions
  156. ------------------------
  157. Q:
  158. What happens if a PCIe device driver does not provide an
  159. error recovery handler (pci_driver->err_handler is equal to NULL)?
  160. A:
  161. The devices attached with the driver won't be recovered. If the
  162. error is fatal, kernel will print out warning messages. Please refer
  163. to section 3 for more information.
  164. Q:
  165. What happens if an upstream port service driver does not provide
  166. callback reset_link?
  167. A:
  168. Fatal error recovery will fail if the errors are reported by the
  169. upstream ports who are attached by the service driver.
  170. Software error injection
  171. ========================
  172. Debugging PCIe AER error recovery code is quite difficult because it
  173. is hard to trigger real hardware errors. Software based error
  174. injection can be used to fake various kinds of PCIe errors.
  175. First you should enable PCIe AER software error injection in kernel
  176. configuration, that is, following item should be in your .config.
  177. CONFIG_PCIEAER_INJECT=y or CONFIG_PCIEAER_INJECT=m
  178. After reboot with new kernel or insert the module, a device file named
  179. /dev/aer_inject should be created.
  180. Then, you need a user space tool named aer-inject, which can be gotten
  181. from:
  182. https://github.com/intel/aer-inject.git
  183. More information about aer-inject can be found in the document in
  184. its source code.