qcom,llcc.yaml 7.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267
  1. # SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
  2. %YAML 1.2
  3. ---
  4. $id: http://devicetree.org/schemas/cache/qcom,llcc.yaml#
  5. $schema: http://devicetree.org/meta-schemas/core.yaml#
  6. title: Last Level Cache Controller
  7. maintainers:
  8. - Bjorn Andersson <andersson@kernel.org>
  9. description: |
  10. LLCC (Last Level Cache Controller) provides last level of cache memory in SoC,
  11. that can be shared by multiple clients. Clients here are different cores in the
  12. SoC, the idea is to minimize the local caches at the clients and migrate to
  13. common pool of memory. Cache memory is divided into partitions called slices
  14. which are assigned to clients. Clients can query the slice details, activate
  15. and deactivate them.
  16. properties:
  17. compatible:
  18. enum:
  19. - qcom,qdu1000-llcc
  20. - qcom,sa8775p-llcc
  21. - qcom,sc7180-llcc
  22. - qcom,sc7280-llcc
  23. - qcom,sc8180x-llcc
  24. - qcom,sc8280xp-llcc
  25. - qcom,sdm845-llcc
  26. - qcom,sm6350-llcc
  27. - qcom,sm7150-llcc
  28. - qcom,sm8150-llcc
  29. - qcom,sm8250-llcc
  30. - qcom,sm8350-llcc
  31. - qcom,sm8450-llcc
  32. - qcom,sm8550-llcc
  33. - qcom,sm8650-llcc
  34. - qcom,x1e80100-llcc
  35. reg:
  36. minItems: 2
  37. maxItems: 10
  38. reg-names:
  39. minItems: 2
  40. maxItems: 10
  41. interrupts:
  42. maxItems: 1
  43. nvmem-cells:
  44. items:
  45. - description: Reference to an nvmem node for multi channel DDR
  46. nvmem-cell-names:
  47. items:
  48. - const: multi-chan-ddr
  49. required:
  50. - compatible
  51. - reg
  52. - reg-names
  53. allOf:
  54. - if:
  55. properties:
  56. compatible:
  57. contains:
  58. enum:
  59. - qcom,sc7180-llcc
  60. - qcom,sm6350-llcc
  61. then:
  62. properties:
  63. reg:
  64. items:
  65. - description: LLCC0 base register region
  66. - description: LLCC broadcast base register region
  67. reg-names:
  68. items:
  69. - const: llcc0_base
  70. - const: llcc_broadcast_base
  71. - if:
  72. properties:
  73. compatible:
  74. contains:
  75. enum:
  76. - qcom,sa8775p-llcc
  77. then:
  78. properties:
  79. reg:
  80. items:
  81. - description: LLCC0 base register region
  82. - description: LLCC1 base register region
  83. - description: LLCC2 base register region
  84. - description: LLCC3 base register region
  85. - description: LLCC4 base register region
  86. - description: LLCC5 base register region
  87. - description: LLCC broadcast base register region
  88. reg-names:
  89. items:
  90. - const: llcc0_base
  91. - const: llcc1_base
  92. - const: llcc2_base
  93. - const: llcc3_base
  94. - const: llcc4_base
  95. - const: llcc5_base
  96. - const: llcc_broadcast_base
  97. - if:
  98. properties:
  99. compatible:
  100. contains:
  101. enum:
  102. - qcom,sc7280-llcc
  103. then:
  104. properties:
  105. reg:
  106. items:
  107. - description: LLCC0 base register region
  108. - description: LLCC1 base register region
  109. - description: LLCC broadcast base register region
  110. reg-names:
  111. items:
  112. - const: llcc0_base
  113. - const: llcc1_base
  114. - const: llcc_broadcast_base
  115. - if:
  116. properties:
  117. compatible:
  118. contains:
  119. enum:
  120. - qcom,qdu1000-llcc
  121. - qcom,sc8180x-llcc
  122. - qcom,sc8280xp-llcc
  123. then:
  124. properties:
  125. reg:
  126. items:
  127. - description: LLCC0 base register region
  128. - description: LLCC1 base register region
  129. - description: LLCC2 base register region
  130. - description: LLCC3 base register region
  131. - description: LLCC4 base register region
  132. - description: LLCC5 base register region
  133. - description: LLCC6 base register region
  134. - description: LLCC7 base register region
  135. - description: LLCC broadcast base register region
  136. reg-names:
  137. items:
  138. - const: llcc0_base
  139. - const: llcc1_base
  140. - const: llcc2_base
  141. - const: llcc3_base
  142. - const: llcc4_base
  143. - const: llcc5_base
  144. - const: llcc6_base
  145. - const: llcc7_base
  146. - const: llcc_broadcast_base
  147. - if:
  148. properties:
  149. compatible:
  150. contains:
  151. enum:
  152. - qcom,x1e80100-llcc
  153. then:
  154. properties:
  155. reg:
  156. items:
  157. - description: LLCC0 base register region
  158. - description: LLCC1 base register region
  159. - description: LLCC2 base register region
  160. - description: LLCC3 base register region
  161. - description: LLCC4 base register region
  162. - description: LLCC5 base register region
  163. - description: LLCC6 base register region
  164. - description: LLCC7 base register region
  165. - description: LLCC broadcast base register region
  166. - description: LLCC broadcast AND register region
  167. reg-names:
  168. items:
  169. - const: llcc0_base
  170. - const: llcc1_base
  171. - const: llcc2_base
  172. - const: llcc3_base
  173. - const: llcc4_base
  174. - const: llcc5_base
  175. - const: llcc6_base
  176. - const: llcc7_base
  177. - const: llcc_broadcast_base
  178. - const: llcc_broadcast_and_base
  179. - if:
  180. properties:
  181. compatible:
  182. contains:
  183. enum:
  184. - qcom,sdm845-llcc
  185. - qcom,sm8150-llcc
  186. - qcom,sm8250-llcc
  187. - qcom,sm8350-llcc
  188. then:
  189. properties:
  190. reg:
  191. items:
  192. - description: LLCC0 base register region
  193. - description: LLCC1 base register region
  194. - description: LLCC2 base register region
  195. - description: LLCC3 base register region
  196. - description: LLCC broadcast base register region
  197. reg-names:
  198. items:
  199. - const: llcc0_base
  200. - const: llcc1_base
  201. - const: llcc2_base
  202. - const: llcc3_base
  203. - const: llcc_broadcast_base
  204. - if:
  205. properties:
  206. compatible:
  207. contains:
  208. enum:
  209. - qcom,sm8450-llcc
  210. - qcom,sm8550-llcc
  211. - qcom,sm8650-llcc
  212. then:
  213. properties:
  214. reg:
  215. items:
  216. - description: LLCC0 base register region
  217. - description: LLCC1 base register region
  218. - description: LLCC2 base register region
  219. - description: LLCC3 base register region
  220. - description: LLCC broadcast OR register region
  221. - description: LLCC broadcast AND register region
  222. reg-names:
  223. items:
  224. - const: llcc0_base
  225. - const: llcc1_base
  226. - const: llcc2_base
  227. - const: llcc3_base
  228. - const: llcc_broadcast_base
  229. - const: llcc_broadcast_and_base
  230. additionalProperties: false
  231. examples:
  232. - |
  233. #include <dt-bindings/interrupt-controller/arm-gic.h>
  234. soc {
  235. #address-cells = <2>;
  236. #size-cells = <2>;
  237. system-cache-controller@1100000 {
  238. compatible = "qcom,sdm845-llcc";
  239. reg = <0 0x01100000 0 0x50000>, <0 0x01180000 0 0x50000>,
  240. <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>,
  241. <0 0x01300000 0 0x50000>;
  242. reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
  243. "llcc3_base", "llcc_broadcast_base";
  244. interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
  245. };
  246. };